| Line 84... |
Line 84... |
#define TRAP_TEST
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#define TRAP_TEST
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#define MPY_TEST
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#define MPY_TEST
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#define PUSH_TEST
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#define PUSH_TEST
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#define PIPELINE_STACK_TEST
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#define PIPELINE_STACK_TEST
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#define MEM_PIPELINE_TEST
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#define MEM_PIPELINE_TEST
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#define NOWAIT_PIPELINE_TEST // Were wait states btwn regs removed properly?
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test:
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test:
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#ifdef DO_TEST_ASSEMBLER
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#ifdef DO_TEST_ASSEMBLER
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; We start out by testing our assembler. We give it some instructions, which
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; We start out by testing our assembler. We give it some instructions, which
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; are then manually checked by disassembling/dumping the result and making
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; are then manually checked by disassembling/dumping the result and making
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; certain they match. This is not an automated test, but it is an important
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; certain they match. This is not an automated test, but it is an important
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| Line 358... |
Line 359... |
second_lsl_overflow_passes:
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second_lsl_overflow_passes:
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// Test carry
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// Test carry
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ldi $0x07000,r11
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ldi $0x07000,r11
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ldi $-1,r0
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ldi $-1,r0
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add $1,r0
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add $1,r0
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tst $2,cc
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tst sys.ccc,cc
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trap.z r11
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trap.z r11
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// and carry from subtraction
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// and carry from subtraction
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ldi $0x08000,r11
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ldi $0x08000,r11
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clr r0
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clr r0
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sub $1,r0
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sub $1,r0
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tst $2,cc
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tst sys.ccc,cc
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trap.z r11
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trap.z r11
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// Carry from right shift
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clr r0 ; r0 = 0
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lsr 1,r0 ; r0 = 0, c = 0
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add.c 1,r0 ; r0 = 0
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cmp 1,r0 ; r0 ?= 1
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trap.z r11
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LDI 1,r0 ; r0 = 1
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lsr 1,r0 ; r0 = 0, c = 1
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add.c 1,r0 ; r0 = 1
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cmp 1,r0
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trap.nz r11
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ldi 0x070eca6,r0
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ldi 0x0408b85,r1
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ldi 0x0387653,r2
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lsr 1,r0
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xor.c r1,r0
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cmp r2,r0
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trap.nz r11
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#endif
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#endif
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#ifdef LOOP_TEST
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#ifdef LOOP_TEST
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// Let's try a loop: for i=0; i<5; i++)
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// Let's try a loop: for i=0; i<5; i++)
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| Line 550... |
Line 570... |
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#ifdef MEM_PIPELINE_TEST
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#ifdef MEM_PIPELINE_TEST
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JSR(mem_pipeline_test,R0)
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JSR(mem_pipeline_test,R0)
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#endif // MEM_PIPELINE_TEST
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#endif // MEM_PIPELINE_TEST
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#ifdef NOWAIT_PIPELINE_TEST
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JSR(nowait_pipeline_test,R0)
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#endif // NOWAIT_PIPELINE_TEST
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// Return success / Test the trap interrupt
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// Return success / Test the trap interrupt
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clr r11
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clr r11
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trap r11
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trap r11
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noop
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noop
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noop
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noop
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| Line 580... |
Line 604... |
POP(R2,SP)
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POP(R2,SP)
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POP(R1,SP)
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POP(R1,SP)
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RET
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RET
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#endif
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#endif
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; The pipeline stack test examines whether or not a series of memory commands
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; can be evaluated right after the other without problems. This depends upon
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; the calling routine to properly set up registers to be tested.
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;
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; This is also an incomplete test, as nothing is done to test how these
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; pipeline reads/writes are affected by condition codes.
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;
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#ifdef PIPELINE_STACK_TEST
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#ifdef PIPELINE_STACK_TEST
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pipeline_stack_test:
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pipeline_stack_test:
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SUB 13,SP
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SUB 13,SP
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STO R0,1(SP)
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STO R0,1(SP)
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STO R1,2(SP)
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STO R1,2(SP)
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| Line 665... |
Line 696... |
LOD 2(SP),R1
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LOD 2(SP),R1
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ADD 4,SP
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ADD 4,SP
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RETN
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RETN
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#endif
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#endif
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;
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; Pipeline stalls have been hideous problems for me. The CPU has been modified
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; with special logic to keep stages from stalling. For the most part, this
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; means that ALU and memory results may be accessed either before or as they
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; are written to the register file. This set of code is designed to test
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; whether this bypass logic works.
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#ifdef NOWAIT_PIPELINE_TEST
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nowait_pipeline_test:
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; Allocate for us some number of registers
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;
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SUB 5,SP
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STO R0,1(SP)
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STO R1,2(SP)
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STO R2,3(SP)
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STO R3,4(SP)
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STO R4,5(SP)
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;
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; Let's start with ALU-ALU testing
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; AA: result->input A
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; AA: result->input B
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; AA: result->input A on condition
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; AA: result->input B on condition
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; AA: result->input B plus offset
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; AA: result->input B plus offset on condition
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;
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; Then we need to do ALU-Mem input testing
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; (not implemented yet)
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; Mem output->ALU input testing
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; (not implemented yet)
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; Mem output->MEM input testing
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; (not implemented yet)
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;
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LOD 1(SP),R0
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LOD 2(SP),R1
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LOD 3(SP),R2
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LOD 4(SP),R3
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LOD 5(SP),R4
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ADD 5,SP
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RETN
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#endif // NOWAIT_PIPELINE_TEST
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fill 512,0
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fill 512,0
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stack: // Must point to a valid word initially
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stack: // Must point to a valid word initially
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word 0
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word 0
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