| Line 24... |
Line 24... |
; more and more capability tests within the file. If the Lord is
|
; more and more capability tests within the file. If the Lord is
|
; willing, this will become the proof that the CPU completely works.
|
; willing, this will become the proof that the CPU completely works.
|
;
|
;
|
;
|
;
|
; Creator: Dan Gisselquist, Ph.D.
|
; Creator: Dan Gisselquist, Ph.D.
|
; Gisselquist Tecnology, LLC
|
; Gisselquist Technology, LLC
|
;
|
;
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
;
|
;
|
; Copyright (C) 2015, Gisselquist Technology, LLC
|
; Copyright (C) 2015, Gisselquist Technology, LLC
|
;
|
;
|
| Line 86... |
Line 86... |
#define PUSH_TEST
|
#define PUSH_TEST
|
#define PIPELINE_STACK_TEST
|
#define PIPELINE_STACK_TEST
|
#define MEM_PIPELINE_TEST
|
#define MEM_PIPELINE_TEST
|
#define CONDITIONAL_EXECUTION_TEST
|
#define CONDITIONAL_EXECUTION_TEST
|
#define NOWAIT_PIPELINE_TEST // Were wait states btwn regs removed properly?
|
#define NOWAIT_PIPELINE_TEST // Were wait states btwn regs removed properly?
|
|
#define BCMEM_TEST // Do memory and conditions work well together?
|
test:
|
test:
|
#ifdef DO_TEST_ASSEMBLER
|
#ifdef DO_TEST_ASSEMBLER
|
; We start out by testing our assembler. We give it some instructions, which
|
; We start out by testing our assembler. We give it some instructions, which
|
; are then manually checked by disassembling/dumping the result and making
|
; are then manually checked by disassembling/dumping the result and making
|
; certain they match. This is not an automated test, but it is an important
|
; certain they match. This is not an automated test, but it is an important
|
| Line 271... |
Line 272... |
trap 0
|
trap 0
|
busy
|
busy
|
traptest_supervisor:
|
traptest_supervisor:
|
mov traptest_user(pc),upc
|
mov traptest_user(pc),upc
|
rtu
|
rtu
|
mov cc,r0
|
mov ucc,r0
|
tst sys.cctrap,r0
|
tst sys.cctrap,r0
|
|
tst.nz sys.gie,r0
|
bz test_failure
|
bz test_failure
|
#endif
|
#endif
|
|
|
testbench:
|
testbench:
|
// Let's build a software test bench.
|
// Let's build a software test bench.
|
| Line 286... |
Line 288... |
mov stack(pc),usp
|
mov stack(pc),usp
|
ldi 0x8000ffff,r0 ; Clear interrupts, turn all vectors off
|
ldi 0x8000ffff,r0 ; Clear interrupts, turn all vectors off
|
sto r0,(r12)
|
sto r0,(r12)
|
rtu
|
rtu
|
mov ucc,r0
|
mov ucc,r0
|
cmp sys.cctrap,r0
|
CMP sys.cctrap+sys.gie,r0
|
bnz test_failure
|
bnz test_failure
|
halt
|
halt
|
// Go into an infinite loop if the trap fails
|
// Go into an infinite loop if the trap fails
|
// Permanent loop instruction -- a busy halt if you will
|
// Permanent loop instruction -- a busy halt if you will
|
test_failure:
|
test_failure:
|
| Line 527... |
Line 529... |
ldi 0x08000,r0
|
ldi 0x08000,r0
|
mpys r0,r0 // R0 now equals 0x40000000
|
mpys r0,r0 // R0 now equals 0x40000000
|
ldi 0x40000000,r1
|
ldi 0x40000000,r1
|
cmp r0,r1
|
cmp r0,r1
|
trap.ne r11
|
trap.ne r11
|
|
//
|
|
// And from our eyeball test ...
|
|
LDI 0x01ff01ff,R0
|
|
MOV R0,R7
|
|
MOV 8(SP),R6
|
|
LSR 7,R0
|
|
AND 7,R0
|
|
LDI 7,R1
|
|
SUB R0,R1
|
|
MOV R1,R0
|
|
MPYU 5,R0
|
|
CMP 20,R0
|
|
TRAP.NE R11
|
#endif
|
#endif
|
|
|
#ifdef PUSH_TEST
|
#ifdef PUSH_TEST
|
ldi $0x0e000,r11 // Mark our test
|
ldi $0x0e000,r11 // Mark our test
|
ldi 0x01248cab,r0
|
ldi 0x01248cab,r0
|
ldi 0xd5312480,r1 // Let's see if we can preserve this as well
|
ldi 0xd5312480,r1 // Let's see if we can preserve this as well
|
mov r1,r7
|
mov r1,r7
|
JSR(reverse_bit_order,R4); // *SP = 0x010013d
|
FJSR(reverse_bit_order,R4); // *SP = 0x010013d
|
cmp r0,r1
|
cmp r0,r1
|
trap.ne r11
|
trap.ne r11
|
cmp r0,r7
|
cmp r0,r7
|
trap.ne r11
|
trap.ne r11
|
#endif
|
#endif
|
| Line 550... |
Line 565... |
MOV 1(R1),R2
|
MOV 1(R1),R2
|
MOV 1(R2),R3
|
MOV 1(R2),R3
|
MOV 1(R3),R4
|
MOV 1(R3),R4
|
MOV 1(R4),R5
|
MOV 1(R4),R5
|
MOV 1(R5),R6
|
MOV 1(R5),R6
|
JSR(pipeline_stack_test,R7)
|
FJSR(pipeline_stack_test,R7)
|
CMP 1,R0
|
CMP 1,R0
|
trap.ne R11
|
trap.ne R11
|
CMP 2,R1
|
CMP 2,R1
|
trap.ne R11
|
trap.ne R11
|
CMP 3,R2
|
CMP 3,R2
|
| Line 568... |
Line 583... |
CMP 7,R6
|
CMP 7,R6
|
trap.ne R11
|
trap.ne R11
|
#endif
|
#endif
|
|
|
#ifdef MEM_PIPELINE_TEST
|
#ifdef MEM_PIPELINE_TEST
|
JSR(mem_pipeline_test,R0)
|
LDI 0x10000,R11
|
|
FJSR(mem_pipeline_test,R0)
|
#endif // MEM_PIPELINE_TEST
|
#endif // MEM_PIPELINE_TEST
|
|
|
#ifdef CONDITIONAL_EXECUTION_TEST
|
#ifdef CONDITIONAL_EXECUTION_TEST
|
JSR(conditional_execution_test,R0)
|
LDI 0x11000,R11
|
|
FJSR(conditional_execution_test,R0)
|
#endif // CONDITIONAL_EXECUTION_TEST
|
#endif // CONDITIONAL_EXECUTION_TEST
|
|
|
#ifdef NOWAIT_PIPELINE_TEST
|
#ifdef NOWAIT_PIPELINE_TEST
|
JSR(nowait_pipeline_test,R0)
|
LDI 0x12000,R11
|
|
FJSR(nowait_pipeline_test,R0)
|
#endif // NOWAIT_PIPELINE_TEST
|
#endif // NOWAIT_PIPELINE_TEST
|
|
|
|
#ifdef BCMEM_TEST
|
|
LDI 0x13000,R11
|
|
CLR R0
|
|
LDI -1,R1
|
|
STO R0,bcmemtestloc(PC)
|
|
LOD bcmemtestloc(PC),R1
|
|
CMP R0,R1
|
|
TRAP.NZ R11
|
|
CMP 0x13000,R11
|
|
BZ bcmemtest_cmploc_1
|
|
STO R11,bcmemtestloc(PC)
|
|
bcmemtest_cmploc_1:
|
|
LOD bcmemtestloc(PC),R0
|
|
CMP R0,R11
|
|
TRAP.Z R11
|
|
CLR R0
|
|
CMP R0,R11
|
|
BZ bcmemtest_cmploc_2
|
|
STO.NZ R11,bcmemtestloc(PC)
|
|
bcmemtest_cmploc_2:
|
|
NOOP
|
|
LOD bcmemtestloc(PC),R0
|
|
CMP R0,R11
|
|
TRAP.NZ R11
|
|
BRA end_bcmemtest
|
|
bcmemtestloc:
|
|
WORD 0
|
|
end_bcmemtest:
|
|
#endif
|
// Return success / Test the trap interrupt
|
// Return success / Test the trap interrupt
|
clr r11
|
clr r11
|
trap r11
|
trap r11
|
noop
|
noop
|
noop
|
noop
|
| Line 593... |
Line 640... |
halt
|
halt
|
|
|
// Now, let's test whether or not we can handle a subroutine
|
// Now, let's test whether or not we can handle a subroutine
|
#ifdef PUSH_TEST
|
#ifdef PUSH_TEST
|
reverse_bit_order:
|
reverse_bit_order:
|
PUSH(R1,SP) ; R1 will be our loop counter
|
SUB 3,SP
|
PUSH(R2,SP) ; R2 will be our accumulator and eventual result
|
STO R1,(SP) ; R1 will be our loop counter
|
|
STO R2,1(SP) ; R2 will be our accumulator and eventual result
|
|
STO R4,2(SP)
|
LDI 32,R1
|
LDI 32,R1
|
CLR R2
|
CLR R2
|
reverse_bit_order_loop:
|
reverse_bit_order_loop:
|
LSL 1,R2
|
LSL 1,R2
|
LSR 1,R0
|
LSR 1,R0
|
OR.C 1,R2
|
OR.C 1,R2
|
SUB 1,R1
|
SUB 1,R1
|
BNZ reverse_bit_order_loop
|
BNZ reverse_bit_order_loop
|
MOV R2,R0
|
MOV R2,R0
|
POP(R2,SP)
|
LOD (SP),R1
|
POP(R1,SP)
|
LOD 1(SP),R2
|
RET
|
LOD 2(SP),R4
|
|
ADD 3,SP
|
|
JMP R4
|
#endif
|
#endif
|
|
|
; The pipeline stack test examines whether or not a series of memory commands
|
; The pipeline stack test examines whether or not a series of memory commands
|
; can be evaluated right after the other without problems. This depends upon
|
; can be evaluated right after the other without problems. This depends upon
|
; the calling routine to properly set up registers to be tested.
|
; the calling routine to properly set up registers to be tested.
|
| Line 619... |
Line 670... |
; pipeline reads/writes are affected by condition codes.
|
; pipeline reads/writes are affected by condition codes.
|
;
|
;
|
#ifdef PIPELINE_STACK_TEST
|
#ifdef PIPELINE_STACK_TEST
|
pipeline_stack_test:
|
pipeline_stack_test:
|
SUB 13,SP
|
SUB 13,SP
|
STO R0,1(SP)
|
STO R0,(SP)
|
STO R1,2(SP)
|
STO R1,1(SP)
|
STO R2,3(SP)
|
STO R2,2(SP)
|
STO R3,4(SP)
|
STO R3,3(SP)
|
STO R4,5(SP)
|
STO R4,4(SP)
|
STO R5,6(SP)
|
STO R5,5(SP)
|
STO R6,7(SP)
|
STO R6,6(SP)
|
STO R7,8(SP)
|
STO R7,7(SP)
|
STO R8,9(SP)
|
STO R8,8(SP)
|
STO R9,10(SP)
|
STO R9,9(SP)
|
STO R10,11(SP)
|
STO R10,10(SP)
|
STO R11,12(SP)
|
STO R11,11(SP)
|
STO R12,13(SP)
|
STO R12,12(SP)
|
XOR -1,R0
|
XOR -1,R0
|
XOR -1,R1
|
XOR -1,R1
|
XOR -1,R2
|
XOR -1,R2
|
XOR -1,R3
|
XOR -1,R3
|
XOR -1,R4
|
XOR -1,R4
|
| Line 645... |
Line 696... |
XOR -1,R8
|
XOR -1,R8
|
XOR -1,R9
|
XOR -1,R9
|
XOR -1,R10
|
XOR -1,R10
|
XOR -1,R11
|
XOR -1,R11
|
XOR -1,R12
|
XOR -1,R12
|
LOD 1(SP),R0
|
LOD (SP),R0
|
LOD 2(SP),R1
|
LOD 1(SP),R1
|
LOD 3(SP),R2
|
LOD 2(SP),R2
|
LOD 4(SP),R3
|
LOD 3(SP),R3
|
LOD 5(SP),R4
|
LOD 4(SP),R4
|
LOD 6(SP),R5
|
LOD 5(SP),R5
|
LOD 7(SP),R6
|
LOD 6(SP),R6
|
LOD 8(SP),R7
|
LOD 7(SP),R7
|
LOD 9(SP),R8
|
LOD 8(SP),R8
|
LOD 10(SP),R9
|
LOD 9(SP),R9
|
LOD 11(SP),R10
|
LOD 10(SP),R10
|
LOD 12(SP),R11
|
LOD 11(SP),R11
|
LOD 13(SP),R12
|
LOD 12(SP),R12
|
ADD 13,SP
|
ADD 13,SP
|
LOD 1(SP),PC
|
JMP R7
|
#endif // PIPELINE_STACK_TEST
|
#endif // PIPELINE_STACK_TEST
|
|
|
#ifdef MEM_PIPELINE_TEST
|
#ifdef MEM_PIPELINE_TEST
|
mem_pipeline_test:
|
mem_pipeline_test:
|
SUB 4,SP
|
SUB 4,SP
|
STO R0,1(SP)
|
STO R0,(SP)
|
STO R1,2(SP)
|
STO R1,1(SP)
|
LDI 0x10000,R11
|
LDI 0x10000,R11
|
;
|
;
|
; Test #1 ... Let's start by writing a value to memory
|
; Test #1 ... Let's start by writing a value to memory
|
LDI -1,R0
|
LDI -1,R0
|
CLR R1
|
CLR R1
|
STO R0,3(SP)
|
STO R0,2(SP)
|
LOD 3(SP),R1
|
LOD 2(SP),R1
|
CMP R1,R0
|
CMP R1,R0
|
MOV.NZ R11,CC
|
MOV.NZ R11,CC
|
|
|
; Test #2, reading and then writing a value from memory
|
; Test #2, reading and then writing a value from memory
|
NOP
|
NOP
|
NOP
|
NOP
|
CLR R0
|
CLR R0
|
CLR R1
|
CLR R1
|
LOD 3(SP),R0 ; This should load back up our -1 value
|
LOD 2(SP),R0 ; This should load back up our -1 value
|
STO R0,4(SP)
|
STO R0,3(SP)
|
; Insist that the pipeline clear
|
; Insist that the pipeline clear
|
LOD 3(SP),R0
|
LOD 2(SP),R0
|
; Now let's try loading into R1
|
; Now let's try loading into R1
|
NOP
|
NOP
|
NOP
|
NOP
|
NOP
|
NOP
|
NOP
|
NOP
|
LOD 4(SP),R1
|
LOD 3(SP),R1
|
CMP R1,R0
|
CMP R1,R0
|
MOV.NZ R11,CC
|
MOV.NZ R11,CC
|
|
|
LOD 1(SP),R0
|
LOD (SP),R0
|
LOD 2(SP),R1
|
LOD 1(SP),R1
|
ADD 4,SP
|
ADD 4,SP
|
RETN
|
JMP R0
|
#endif
|
#endif
|
|
|
#ifdef CONDITIONAL_EXECUTION_TEST
|
#ifdef CONDITIONAL_EXECUTION_TEST
|
conditional_execution_test:
|
conditional_execution_test:
|
; R0 is corrupt on entry, no need to save it
|
SUB 1,SP
|
; SUB 1,SP
|
STO R0,(SP)
|
; STO R0,1(SP)
|
;
|
|
|
CLRF R0
|
CLRF R0
|
ADD.Z 1,R0
|
ADD.Z 1,R0
|
TRAP.NZ R11
|
TRAP.NZ R11
|
CMP.Z 0,R0
|
CMP.Z 0,R0
|
TRAP.Z R11
|
TRAP.Z R11
|
|
|
; LOD 1(SP),R0
|
LOD (SP),R0
|
; ADD 1,SP
|
ADD 1,SP
|
; ; Stall
|
JMP R0
|
RETN
|
|
#endif
|
#endif
|
|
|
;
|
;
|
; Pipeline stalls have been hideous problems for me. The CPU has been modified
|
; Pipeline stalls have been hideous problems for me. The CPU has been modified
|
; with special logic to keep stages from stalling. For the most part, this
|
; with special logic to keep stages from stalling. For the most part, this
|
| Line 732... |
Line 781... |
; Allocate for us some number of registers
|
; Allocate for us some number of registers
|
;
|
;
|
SUB 6,SP
|
SUB 6,SP
|
; Leave a spot open on the stack for a local variable,
|
; Leave a spot open on the stack for a local variable,
|
; kept in memory.
|
; kept in memory.
|
STO R0,2(SP)
|
STO R0,(SP)
|
STO R1,3(SP)
|
STO R1,1(SP)
|
STO R2,4(SP)
|
STO R2,2(SP)
|
STO R3,5(SP)
|
STO R3,3(SP)
|
STO R4,6(SP)
|
STO R4,4(SP)
|
;
|
;
|
; Let's start with ALU-ALU testing
|
; Let's start with ALU-ALU testing
|
; AA: result->input A
|
; AA: result->input A
|
CLR R0
|
CLR R0
|
ADD 1,R0
|
ADD 1,R0
|
| Line 783... |
Line 832... |
|
|
;
|
;
|
; Then we need to do ALU-Mem input testing
|
; Then we need to do ALU-Mem input testing
|
;
|
;
|
CLR R0
|
CLR R0
|
STO R0,1(SP)
|
STO R0,5(SP)
|
LDI 8352,R0
|
LDI 8352,R0
|
LOD 1(SP),R0
|
LOD 5(SP),R0
|
TST -1,R0
|
TST -1,R0
|
TRAP.NZ R11
|
TRAP.NZ R11
|
|
|
LDI 937,R0 ; Let's try again, this time something that's
|
LDI 937,R0 ; Let's try again, this time something that's
|
STO R0,1(SP) ; not zero
|
STO R0,5(SP) ; not zero
|
NOOP
|
NOOP
|
LOD 1(SP),R0
|
LOD 5(SP),R0
|
CMP 938,R0 ; Let's not compare with self, let's that
|
CMP 938,R0 ; Let's not compare with self, let's that
|
TRAP.GE R11 ; masks a problem--compare with a different
|
TRAP.GE R11 ; masks a problem--compare with a different
|
CMP 936,R0 ; number instead.
|
CMP 936,R0 ; number instead.
|
TRAP.LT R11
|
TRAP.LT R11
|
|
|
; Mem output->ALU input testing
|
; Mem output->ALU input testing
|
; We just did that as partof our last test
|
; We just did that as partof our last test
|
; Mem output->MEM input testing
|
; Mem output->MEM input testing
|
;
|
;
|
LDI 5328,R2
|
LDI 5328,R2
|
LOD 1(SP),R2
|
LOD 5(SP),R2
|
STO R2,1(SP)
|
STO R2,5(SP)
|
LOD 1(SP),R1
|
LOD 5(SP),R1
|
CMP 937,R1
|
CMP 937,R1
|
TRAP.NZ R11
|
TRAP.NZ R11
|
;
|
;
|
LOD 2(SP),R0
|
LOD (SP),R0
|
LOD 3(SP),R1
|
LOD 1(SP),R1
|
LOD 4(SP),R2
|
LOD 2(SP),R2
|
LOD 5(SP),R3
|
LOD 3(SP),R3
|
LOD 6(SP),R4
|
LOD 4(SP),R4
|
ADD 6,SP
|
ADD 6,SP
|
RETN
|
JMP R0
|
#endif // NOWAIT_PIPELINE_TEST
|
#endif // NOWAIT_PIPELINE_TEST
|
|
|
|
|
fill 512,0
|
fill 512,0
|
stack: // Must point to a valid word initially
|
stack: // Must point to a valid word initially
|
word 0
|
word 0
|
