URL
https://opencores.org/ocsvn/zx_ula/zx_ula/trunk
Show entire file |
Details |
Blame |
View Log
Rev 24 |
Rev 25 |
Line 1874... |
Line 1874... |
I_RETN <= '1';
|
I_RETN <= '1';
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
|
when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
|
-- IN r,(C)
|
-- IN r,(C)
|
MCycles <= "011"; -- Should be 3 MCycles (mcleod_ideafix)
|
MCycles <= "010";
|
case to_integer(unsigned(MCycle)) is
|
case to_integer(unsigned(MCycle)) is
|
when 2 =>
|
when 1 =>
|
Set_Addr_To <= aBC;
|
Set_Addr_To <= aBC;
|
when 3 =>
|
when 2 =>
|
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
|
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
|
IORQ <= '1';
|
IORQ <= '1';
|
if IR(5 downto 3) /= "110" then
|
if IR(5 downto 3) /= "110" then
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Set_BusA_To(2 downto 0) <= IR(5 downto 3);
|
Set_BusA_To(2 downto 0) <= IR(5 downto 3);
|
Line 1891... |
Line 1891... |
when others =>
|
when others =>
|
end case;
|
end case;
|
when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
|
when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
|
-- OUT (C),r
|
-- OUT (C),r
|
-- OUT (C),0
|
-- OUT (C),0
|
MCycles <= "011"; -- Should be 3 MCycles (mcleod_ideafix)
|
MCycles <= "010";
|
case to_integer(unsigned(MCycle)) is
|
case to_integer(unsigned(MCycle)) is
|
when 2 =>
|
when 1 =>
|
Set_Addr_To <= aBC;
|
Set_Addr_To <= aBC;
|
Set_BusB_To(2 downto 0) <= IR(5 downto 3);
|
Set_BusB_To(2 downto 0) <= IR(5 downto 3);
|
if IR(5 downto 3) = "110" then
|
if IR(5 downto 3) = "110" then
|
Set_BusB_To(3) <= '1';
|
Set_BusB_To(3) <= '1';
|
end if;
|
end if;
|
when 3 =>
|
when 2 =>
|
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
|
TStates <= "100"; -- MIKEJ should be 4 for IO cycle
|
Write <= '1';
|
Write <= '1';
|
IORQ <= '1';
|
IORQ <= '1';
|
when others =>
|
when others =>
|
end case;
|
end case;
|
Line 1967... |
Line 1967... |
IORQ <= '1';
|
IORQ <= '1';
|
Write <= '1';
|
Write <= '1';
|
I_BTR <= '1';
|
I_BTR <= '1';
|
when 4 =>
|
when 4 =>
|
NoRead <= '1';
|
NoRead <= '1';
|
TStates <= "100"; -- Was "101", to make OUTI to last 16 t-cycles (mcleod_ideafix)
|
TStates <= "101";
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end case;
|
end case;
|
|
|
end case;
|
end case;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.