Line 359... |
Line 359... |
rRGBULAPlus = (ULAPlusPixel)? ULAPlusInkOut : ULAPlusPaperOut;
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rRGBULAPlus = (ULAPlusPixel)? ULAPlusInkOut : ULAPlusPaperOut;
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else
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else
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rRGBULAPlus = 8'h00;
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rRGBULAPlus = 8'h00;
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end
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end
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// CPU contention
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// CPU contention handler (Altwasser version)
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/////////////////////////////////////////////////////////////////////
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reg CPUClk = 0;
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reg CPUClk = 0;
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assign clkcpu = CPUClk;
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assign clkcpu = CPUClk;
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reg ioreqtw3 = 0;
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reg ioreqtw3 = 0;
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reg mreqt23 = 0;
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reg mreqt23 = 0;
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wire ioreq_n = (a[0] | iorq_n) & ~dataportsel & ~addrportsel;
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wire ioreq_n = (a[0] | iorq_n) & ~dataportsel & ~addrportsel;
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Line 376... |
Line 377... |
~CPUClk |
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~CPUClk |
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ioreq_n |
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ioreq_n |
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~ioreqtw3;
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~ioreqtw3;
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wire CLKContention = ~Nor1 | ~Nor2;
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wire CLKContention = ~Nor1 | ~Nor2;
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always @(posedge CPUClk) begin
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ioreqtw3 <= ioreq_n;
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mreqt23 <= mreq_n;
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end
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/////////////////////////////////////////////////////////////////////
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// // CPU contention handler (Chris version)
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// /////////////////////////////////////////////////////////////////////
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// reg CPUClk = 0;
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// assign clkcpu = CPUClk;
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// wire ioreq_n = (a[0] | iorq_n) & ~dataportsel & ~addrportsel;
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// reg ULANotReadingVRAM = 1;
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// reg CycleMayContend = 0;
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//
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// always @(negedge clk7) begin
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// ULANotReadingVRAM <= ~Border_n | (~hc[2] & ~hc[3]);
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// end
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// always @(posedge CPUClk) begin
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// CycleMayContend <= ioreq_n & mreq_n;
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// end
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// wire CLKContention = ~(ULANotReadingVRAM | (((~a[14] | a[15]) & ioreq_n) | ~CycleMayContend));
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// /////////////////////////////////////////////////////////////////////
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|
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// // CPU modified contention handler for broken IO bus cycle of T80 core (Chris version)
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// /////////////////////////////////////////////////////////////////////
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// reg CPUClk = 0;
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// assign clkcpu = CPUClk;
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// wire ioreq_n = (a[0] | iorq_n) & ~dataportsel & ~addrportsel;
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// reg ULANotReadingVRAM = 1;
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// reg CycleMayContend = 0;
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//
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// always @(negedge clk7) begin
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// ULANotReadingVRAM <= ~Border_n | (~hc[2] & ~hc[3]);
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// end
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// always @(posedge CPUClk) begin
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// CycleMayContend <= (ioreq_n | CPUClk) & mreq_n;
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// end
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// wire CLKContention = ~(ULANotReadingVRAM | (((~a[14] | a[15]) & (ioreq_n | ~CPUClk)) | ~CycleMayContend));
|
|
// /////////////////////////////////////////////////////////////////////
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|
|
always @(posedge clk7) begin // change clk7 by clk14 for 7MHz CPU clock operation
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always @(posedge clk7) begin // change clk7 by clk14 for 7MHz CPU clock operation
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if (CPUClk && !CLKContention) // if there's no contention, the clock can go low
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if (CPUClk && !CLKContention) // if there's no contention, the clock can go low
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CPUClk <= 0;
|
CPUClk <= 0;
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else
|
else
|
CPUClk <= 1;
|
CPUClk <= 1;
|
end
|
end
|
always @(posedge CPUClk) begin
|
|
ioreqtw3 <= ioreq_n;
|
|
mreqt23 <= mreq_n;
|
|
end
|
|
|
|
// ULA+ : palette management
|
// ULA+ : palette management
|
always @(posedge clk7 or posedge reset) begin
|
always @(posedge clk7 or posedge reset) begin
|
if (reset)
|
if (reset)
|
ULAPlusConfig <= 0;
|
ULAPlusConfig <= 0;
|
Line 400... |
Line 437... |
ULAPlusConfig <= din[0];
|
ULAPlusConfig <= din[0];
|
end
|
end
|
end
|
end
|
|
|
// ULA-CPU interface
|
// ULA-CPU interface
|
assign dout = (!a[15] && a[14] && !mreq_n)? vramdout : // CPU reads VRAM through ULA as in the +3, not directly
|
assign dout = (!a[15] && a[14] && !mreq_n && !rd_n)? vramdout : // CPU reads VRAM through ULA as in the +3, not directly
|
(!iorq_n && !a[0])? {1'b1,ear,1'b1,kbcolumns} : // CPU reads keyboard and EAR state
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(!iorq_n && !a[0] && !rd_n)? {1'b1,ear,1'b1,kbcolumns} : // CPU reads keyboard and EAR state
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(!iorq_n && a[7:0]==8'hFF && !rd_n)? {6'b000000,TimexHiColorMode,1'b0} : // Timex hicolor config port. Only bit 1 is reported.
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(!iorq_n && a[7:0]==8'hFF && !rd_n)? {6'b000000,TimexHiColorMode,1'b0} : // Timex hicolor config port. Only bit 1 is reported.
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(addrportsel && !rd_n)? ULAPlusAddrReg : // ULA+ addr register
|
(addrportsel && !rd_n)? ULAPlusAddrReg : // ULA+ addr register
|
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b01)? {7'b0000000, ULAPlusConfig} :
|
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b01)? {7'b0000000, ULAPlusConfig} :
|
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b00)? palettedout :
|
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b00)? palettedout :
|
(Border_n)? AttrReg : // to emulate
|
(Border_n)? AttrReg : // to emulate
|