| Line 359... |
Line 359... |
rRGBULAPlus = (ULAPlusPixel)? ULAPlusInkOut : ULAPlusPaperOut;
|
rRGBULAPlus = (ULAPlusPixel)? ULAPlusInkOut : ULAPlusPaperOut;
|
else
|
else
|
rRGBULAPlus = 8'h00;
|
rRGBULAPlus = 8'h00;
|
end
|
end
|
|
|
// CPU contention
|
// CPU contention handler (Altwasser version)
|
|
/////////////////////////////////////////////////////////////////////
|
reg CPUClk = 0;
|
reg CPUClk = 0;
|
assign clkcpu = CPUClk;
|
assign clkcpu = CPUClk;
|
reg ioreqtw3 = 0;
|
reg ioreqtw3 = 0;
|
reg mreqt23 = 0;
|
reg mreqt23 = 0;
|
wire ioreq_n = (a[0] | iorq_n) & ~dataportsel & ~addrportsel;
|
wire ioreq_n = (a[0] | iorq_n) & ~dataportsel & ~addrportsel;
|
| Line 376... |
Line 377... |
~CPUClk |
|
~CPUClk |
|
ioreq_n |
|
ioreq_n |
|
~ioreqtw3;
|
~ioreqtw3;
|
wire CLKContention = ~Nor1 | ~Nor2;
|
wire CLKContention = ~Nor1 | ~Nor2;
|
|
|
|
always @(posedge CPUClk) begin
|
|
ioreqtw3 <= ioreq_n;
|
|
mreqt23 <= mreq_n;
|
|
end
|
|
/////////////////////////////////////////////////////////////////////
|
|
|
|
// // CPU contention handler (Chris version)
|
|
// /////////////////////////////////////////////////////////////////////
|
|
// reg CPUClk = 0;
|
|
// assign clkcpu = CPUClk;
|
|
// wire ioreq_n = (a[0] | iorq_n) & ~dataportsel & ~addrportsel;
|
|
// reg ULANotReadingVRAM = 1;
|
|
// reg CycleMayContend = 0;
|
|
//
|
|
// always @(negedge clk7) begin
|
|
// ULANotReadingVRAM <= ~Border_n | (~hc[2] & ~hc[3]);
|
|
// end
|
|
// always @(posedge CPUClk) begin
|
|
// CycleMayContend <= ioreq_n & mreq_n;
|
|
// end
|
|
// wire CLKContention = ~(ULANotReadingVRAM | (((~a[14] | a[15]) & ioreq_n) | ~CycleMayContend));
|
|
// /////////////////////////////////////////////////////////////////////
|
|
|
|
// // CPU modified contention handler for broken IO bus cycle of T80 core (Chris version)
|
|
// /////////////////////////////////////////////////////////////////////
|
|
// reg CPUClk = 0;
|
|
// assign clkcpu = CPUClk;
|
|
// wire ioreq_n = (a[0] | iorq_n) & ~dataportsel & ~addrportsel;
|
|
// reg ULANotReadingVRAM = 1;
|
|
// reg CycleMayContend = 0;
|
|
//
|
|
// always @(negedge clk7) begin
|
|
// ULANotReadingVRAM <= ~Border_n | (~hc[2] & ~hc[3]);
|
|
// end
|
|
// always @(posedge CPUClk) begin
|
|
// CycleMayContend <= (ioreq_n | CPUClk) & mreq_n;
|
|
// end
|
|
// wire CLKContention = ~(ULANotReadingVRAM | (((~a[14] | a[15]) & (ioreq_n | ~CPUClk)) | ~CycleMayContend));
|
|
// /////////////////////////////////////////////////////////////////////
|
|
|
always @(posedge clk7) begin // change clk7 by clk14 for 7MHz CPU clock operation
|
always @(posedge clk7) begin // change clk7 by clk14 for 7MHz CPU clock operation
|
if (CPUClk && !CLKContention) // if there's no contention, the clock can go low
|
if (CPUClk && !CLKContention) // if there's no contention, the clock can go low
|
CPUClk <= 0;
|
CPUClk <= 0;
|
else
|
else
|
CPUClk <= 1;
|
CPUClk <= 1;
|
end
|
end
|
always @(posedge CPUClk) begin
|
|
ioreqtw3 <= ioreq_n;
|
|
mreqt23 <= mreq_n;
|
|
end
|
|
|
|
// ULA+ : palette management
|
// ULA+ : palette management
|
always @(posedge clk7 or posedge reset) begin
|
always @(posedge clk7 or posedge reset) begin
|
if (reset)
|
if (reset)
|
ULAPlusConfig <= 0;
|
ULAPlusConfig <= 0;
|
| Line 400... |
Line 437... |
ULAPlusConfig <= din[0];
|
ULAPlusConfig <= din[0];
|
end
|
end
|
end
|
end
|
|
|
// ULA-CPU interface
|
// ULA-CPU interface
|
assign dout = (!a[15] && a[14] && !mreq_n)? vramdout : // CPU reads VRAM through ULA as in the +3, not directly
|
assign dout = (!a[15] && a[14] && !mreq_n && !rd_n)? vramdout : // CPU reads VRAM through ULA as in the +3, not directly
|
(!iorq_n && !a[0])? {1'b1,ear,1'b1,kbcolumns} : // CPU reads keyboard and EAR state
|
(!iorq_n && !a[0] && !rd_n)? {1'b1,ear,1'b1,kbcolumns} : // CPU reads keyboard and EAR state
|
(!iorq_n && a[7:0]==8'hFF && !rd_n)? {6'b000000,TimexHiColorMode,1'b0} : // Timex hicolor config port. Only bit 1 is reported.
|
(!iorq_n && a[7:0]==8'hFF && !rd_n)? {6'b000000,TimexHiColorMode,1'b0} : // Timex hicolor config port. Only bit 1 is reported.
|
(addrportsel && !rd_n)? ULAPlusAddrReg : // ULA+ addr register
|
(addrportsel && !rd_n)? ULAPlusAddrReg : // ULA+ addr register
|
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b01)? {7'b0000000, ULAPlusConfig} :
|
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b01)? {7'b0000000, ULAPlusConfig} :
|
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b00)? palettedout :
|
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b00)? palettedout :
|
(Border_n)? AttrReg : // to emulate
|
(Border_n)? AttrReg : // to emulate
|
