| Line 4... |
Line 4... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : lcd16x2_ctrl.vhd
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-- File : lcd16x2_ctrl.vhd
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-- Author : <stachelsau@T420>
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-- Author : <stachelsau@T420>
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-- Company :
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-- Company :
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-- Created : 2012-07-28
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-- Created : 2012-07-28
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-- Last update: 2012-07-29
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-- Last update: 2012-11-28
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-- Platform :
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-- Platform :
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-- Standard : VHDL'93/02
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description: The controller initializes the display when rst goes to '0'.
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-- Description: The controller initializes the display when rst goes to '0'.
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-- After that it writes the contend of the input signals
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-- After that it writes the contend of the input signals
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| Line 60... |
Line 60... |
rs : std_logic;
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rs : std_logic;
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data : std_logic_vector(7 downto 0);
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data : std_logic_vector(7 downto 0);
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delay_h : integer range 0 to MAX_DELAY;
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delay_h : integer range 0 to MAX_DELAY;
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delay_l : integer range 0 to MAX_DELAY;
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delay_l : integer range 0 to MAX_DELAY;
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end record op_t;
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end record op_t;
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constant default : op_t := (rs => '1', data => X"00", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US);
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constant default_op : op_t := (rs => '1', data => X"00", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US);
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constant op_select_line1 : op_t := (rs => '0', data => X"80", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US);
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constant op_select_line1 : op_t := (rs => '0', data => X"80", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US);
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constant op_select_line2 : op_t := (rs => '0', data => X"C0", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US);
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constant op_select_line2 : op_t := (rs => '0', data => X"C0", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US);
|
|
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-- init + config operations:
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-- init + config operations:
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-- write 3 x 0x3 followed by 0x2
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-- write 3 x 0x3 followed by 0x2
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| Line 115... |
Line 115... |
|
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proc_state : process(state, op_state, ptr, line1_buffer, line2_buffer) is
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proc_state : process(state, op_state, ptr, line1_buffer, line2_buffer) is
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begin
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begin
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case state is
|
case state is
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when RESET =>
|
when RESET =>
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this_op <= default;
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this_op <= default_op;
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next_state <= CONFIG;
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next_state <= CONFIG;
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next_ptr <= config_ops_t'high;
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next_ptr <= config_ops_t'high;
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|
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when CONFIG =>
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when CONFIG =>
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this_op <= config_ops(ptr);
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this_op <= config_ops(ptr);
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| Line 140... |
Line 140... |
else
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else
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next_state <= SELECT_LINE1;
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next_state <= SELECT_LINE1;
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end if;
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end if;
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|
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when WRITE_LINE1 =>
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when WRITE_LINE1 =>
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this_op <= default;
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this_op <= default_op;
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this_op.data <= line1_buffer(ptr*8 + 7 downto ptr*8);
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this_op.data <= line1_buffer(ptr*8 + 7 downto ptr*8);
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next_ptr <= ptr;
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next_ptr <= ptr;
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next_state <= WRITE_LINE1;
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next_state <= WRITE_LINE1;
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if op_state = DONE then
|
if op_state = DONE then
|
next_ptr <= ptr - 1;
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next_ptr <= ptr - 1;
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| Line 161... |
Line 161... |
else
|
else
|
next_state <= SELECT_LINE2;
|
next_state <= SELECT_LINE2;
|
end if;
|
end if;
|
|
|
when WRITE_LINE2 =>
|
when WRITE_LINE2 =>
|
this_op <= default;
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this_op <= default_op;
|
this_op.data <= line2_buffer(ptr*8 + 7 downto ptr*8);
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this_op.data <= line2_buffer(ptr*8 + 7 downto ptr*8);
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next_ptr <= ptr;
|
next_ptr <= ptr;
|
next_state <= WRITE_LINE2;
|
next_state <= WRITE_LINE2;
|
if op_state = DONE then
|
if op_state = DONE then
|
next_ptr <= ptr - 1;
|
next_ptr <= ptr - 1;
|
