| Line 47... |
Line 47... |
reg k_forced_mem_size; // used to force the size of a memory read to be 16 bits, used for vector fetch
|
reg k_forced_mem_size; // used to force the size of a memory read to be 16 bits, used for vector fetch
|
/****
|
/****
|
* Decoder outputs
|
* Decoder outputs
|
*/
|
*/
|
wire [2:0] dec_o_p1_mode; // addressing mode
|
wire [2:0] dec_o_p1_mode; // addressing mode
|
wire [2:0] dec_o_p1_optype; // k_opcode type
|
|
wire dec_o_use_s; // signals when S should be used instead of U
|
wire dec_o_use_s; // signals when S should be used instead of U
|
wire dec_o_alu_size; /* size of the result of an alu opcode (destination to be written) */
|
wire dec_o_alu_size; /* size of the result of an alu opcode (destination to be written) */
|
|
wire op_SYNC, op_EXG, op_TFR, op_RTS, op_RTI, op_CWAI;
|
|
wire op_MUL, op_SWI, op_PUSH, op_PULL, op_LEA, op_JMP, op_JSR;
|
|
|
/* ea decoder */
|
/* ea decoder */
|
wire dec_o_ea_ofs8, dec_o_ea_ofs16, dec_o_ea_wpost, dec_o_ea_ofs0, dec_o_ea_indirect;
|
wire dec_o_ea_ofs8, dec_o_ea_ofs16, dec_o_ea_wpost, dec_o_ea_ofs0, dec_o_ea_indirect;
|
/* alu k_opcode decoder */
|
/* alu k_opcode decoder */
|
wire [4:0] dec_o_alu_opcode;
|
wire [4:0] dec_o_alu_opcode;
|
wire [1:0] dec_o_right_path_mod; /* Modifier for alu's right path input */
|
wire [1:0] dec_o_right_path_mod; /* Modifier for alu's right path input */
|
| Line 65... |
Line 67... |
/* test condition */
|
/* test condition */
|
wire dec_o_cond_taken;
|
wire dec_o_cond_taken;
|
/* ALU outputs */
|
/* ALU outputs */
|
wire [15:0] alu_o_result;
|
wire [15:0] alu_o_result;
|
wire [7:0] alu_o_CCR;
|
wire [7:0] alu_o_CCR;
|
wire [7:0] alu8_o_result;
|
|
wire [7:0] alu8_o_CCR;
|
|
/* Register Module outputs */
|
/* Register Module outputs */
|
wire [15:0] regs_o_left_path_data, regs_o_right_path_data, regs_o_eamem_addr, regs_o_su;
|
wire [15:0] regs_o_left_path_data, regs_o_right_path_data, regs_o_eamem_addr, regs_o_su;
|
wire [7:0] regs_o_dp;
|
wire [7:0] regs_o_dp;
|
wire [15:0] regs_o_pc;
|
wire [15:0] regs_o_pc;
|
wire [7:0] regs_o_CCR;
|
wire [7:0] regs_o_CCR;
|
| Line 181... |
Line 181... |
.opcode(k_opcode),
|
.opcode(k_opcode),
|
.postbyte0(k_postbyte),
|
.postbyte0(k_postbyte),
|
.page2_valid(k_p2_valid),
|
.page2_valid(k_p2_valid),
|
.page3_valid(k_p3_valid),
|
.page3_valid(k_p3_valid),
|
.mode(dec_o_p1_mode),
|
.mode(dec_o_p1_mode),
|
.optype(dec_o_p1_optype),
|
.op_SYNC(op_SYNC),
|
|
.op_EXG (op_EXG ),
|
|
.op_TFR (op_TFR ),
|
|
.op_RTS (op_RTS ),
|
|
.op_RTI (op_RTI ),
|
|
.op_CWAI(op_CWAI),
|
|
.op_MUL (op_MUL ),
|
|
.op_SWI (op_SWI ),
|
|
.op_PUSH(op_PUSH),
|
|
.op_PULL(op_PULL),
|
|
.op_LEA (op_LEA ),
|
|
.op_JSR (op_JSR ),
|
|
.op_JMP (op_JMP ),
|
.use_s(dec_o_use_s)
|
.use_s(dec_o_use_s)
|
);
|
);
|
|
|
decode_ea dec_ea(
|
decode_ea dec_ea(
|
.eapostbyte( k_ind_ea ),
|
.eapostbyte( k_ind_ea ),
|
| Line 251... |
Line 263... |
* selects the source to write to register. 16 bit registers have to be written at once after reading the low byte
|
* selects the source to write to register. 16 bit registers have to be written at once after reading the low byte
|
*
|
*
|
*/
|
*/
|
always @(*)
|
always @(*)
|
begin
|
begin
|
datamux_o_dest = alu_o_result;
|
if (op_PULL | op_RTS | op_RTI) // destination register
|
case (dec_o_p1_optype)
|
|
`OP_PULL, `OP_RTS: // destination register
|
|
datamux_o_dest = { k_memhi, k_memlo };
|
datamux_o_dest = { k_memhi, k_memlo };
|
`OP_LEA:
|
else
|
|
if (op_LEA)
|
|
begin
|
if (dec_o_ea_indirect)// & dec_o_alu_size)
|
if (dec_o_ea_indirect)// & dec_o_alu_size)
|
datamux_o_dest = { k_memhi, k_memlo };
|
datamux_o_dest = { k_memhi, k_memlo };
|
else
|
else
|
datamux_o_dest = regs_o_eamem_addr;
|
datamux_o_dest = regs_o_eamem_addr;
|
endcase
|
end
|
|
else
|
|
datamux_o_dest = alu_o_result;
|
end
|
end
|
|
|
/* ALU left input mux */
|
/* ALU left input mux */
|
|
|
always @(*)
|
always @(*)
|
begin
|
begin
|
if (dec_lo_left_path_addr == `RN_MEM8)
|
if (dec_lo_left_path_addr == `RN_MEM8)
|
datamux_o_alu_in_left_path_data = { k_memhi, k_memlo };
|
datamux_o_alu_in_left_path_data = { k_memhi, k_memlo };
|
else
|
else
|
case (dec_o_p1_optype)
|
if (op_LEA)
|
`OP_LEA:
|
begin
|
if (dec_o_ea_indirect)// & dec_o_alu_size)
|
if (dec_o_ea_indirect)// & dec_o_alu_size)
|
datamux_o_alu_in_left_path_data = { k_memhi, k_memlo };
|
datamux_o_alu_in_left_path_data = { k_memhi, k_memlo };
|
else
|
else
|
datamux_o_alu_in_left_path_data = regs_o_eamem_addr;
|
datamux_o_alu_in_left_path_data = regs_o_eamem_addr;
|
default:
|
end
|
|
else
|
datamux_o_alu_in_left_path_data = regs_o_left_path_data;
|
datamux_o_alu_in_left_path_data = regs_o_left_path_data;
|
endcase
|
|
end
|
end
|
/* PC as destination from jmp/bsr mux */
|
/* PC as destination from jmp/bsr mux */
|
always @(*)
|
always @(*)
|
begin
|
begin
|
k_new_pc = { k_memhi,k_memlo }; // used to fetch reset vector
|
k_new_pc = { k_memhi,k_memlo }; // used to fetch reset vector
|
| Line 332... |
Line 346... |
k_reg_firq <= 0;
|
k_reg_firq <= 0;
|
k_reg_irq <= 0;
|
k_reg_irq <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
/* Inrerrupt recognition and acknowledge */
|
/* Interrupt recognition and acknowledge */
|
if (!k_reg_nmi[2])
|
if (!k_reg_nmi[2])
|
k_reg_nmi <= { k_reg_nmi[1:0], cpu_nmi_n };
|
k_reg_nmi <= { k_reg_nmi[1:0], cpu_nmi_n };
|
if (!k_reg_irq[2])
|
if (!k_reg_irq[2])
|
k_reg_irq <= { k_reg_irq[1:0], cpu_irq_n };
|
k_reg_irq <= { k_reg_irq[1:0], cpu_irq_n };
|
if (!k_reg_firq[2])
|
if (!k_reg_firq[2])
|
| Line 526... |
Line 540... |
* ALU opcodes need routing of registers to/from the ALU to the registers
|
* ALU opcodes need routing of registers to/from the ALU to the registers
|
*/
|
*/
|
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`NONE: // unknown opcode or push/pull... refetch ?
|
`NONE: // unknown opcode or push/pull... refetch ?
|
begin
|
begin
|
casex (k_opcode)
|
if (op_SYNC) state <= `SEQ_SYNC;
|
8'h13: state <= `SEQ_SYNC;
|
else if (op_PUSH) // PUSH S&U
|
8'h39: // RTS
|
|
begin
|
|
state <= `SEQ_PREPULL;
|
|
k_pp_regs <= 8'h80; // Pull PC (RTS)all regs
|
|
end
|
|
8'b001101x0: // PUSH S&U
|
|
begin
|
begin
|
state <= `SEQ_PC_READ_L;
|
state <= `SEQ_PC_READ_L;
|
next_state <= `SEQ_PREPUSH;
|
next_state <= `SEQ_PREPUSH;
|
next_push_state <= `SEQ_FETCH;
|
next_push_state <= `SEQ_FETCH;
|
end
|
end
|
8'b001101x1: // PULL S&U
|
else if (op_PULL) // PULL S&U
|
begin
|
begin
|
next_state <= `SEQ_PREPULL;
|
next_state <= `SEQ_PREPULL;
|
state <= `SEQ_PC_READ_L;
|
state <= `SEQ_PC_READ_L;
|
end
|
end
|
8'h3B: // RTI
|
else /* we ignore unknown opcodes */
|
begin
|
|
state <= `SEQ_PREPULL;
|
|
k_pp_regs <= 8'hff; // all regs
|
|
end
|
|
default: /* we ignore unknown opcodes */
|
|
state <= `SEQ_FETCH;
|
state <= `SEQ_FETCH;
|
endcase
|
|
end
|
end
|
`IMMEDIATE: // 8 or 16 bits as result decides..
|
`IMMEDIATE: // 8 or 16 bits as result decides..
|
begin
|
begin
|
if (dec_o_alu_size)
|
if (dec_o_alu_size)
|
state <= `SEQ_PC_READ_H;
|
state <= `SEQ_PC_READ_H;
|
| Line 563... |
Line 565... |
state <= `SEQ_PC_READ_L;
|
state <= `SEQ_PC_READ_L;
|
next_state <= `SEQ_GRAL_ALU;
|
next_state <= `SEQ_GRAL_ALU;
|
end
|
end
|
`INHERENT:
|
`INHERENT:
|
begin
|
begin
|
case (k_opcode)
|
if (op_RTI) // RTI
|
8'h3d: begin k_mul_cnt <= 1'h1; state <= `SEQ_GRAL_ALU; end // counter for mul
|
begin
|
8'h3f: state <= `SEQ_SWI;
|
state <= `SEQ_PREPULL;
|
default: state <= `SEQ_GRAL_ALU;
|
k_pp_regs <= 8'hff; // all regs
|
endcase
|
end
|
|
else if (op_RTS)
|
|
begin
|
|
state <= `SEQ_PREPULL;
|
|
k_pp_regs <= 8'h80; // Pull PC (RTS)all regs
|
|
end
|
|
else if (op_MUL)
|
|
begin k_mul_cnt <= 1'h1; state <= `SEQ_GRAL_ALU; end // counter for mul
|
|
else if (op_SWI)
|
|
state <= `SEQ_SWI;
|
|
else
|
|
state <= `SEQ_GRAL_ALU;
|
end
|
end
|
`DIRECT:
|
`DIRECT:
|
begin
|
begin
|
state <= `SEQ_PC_READ_L; // loads address
|
state <= `SEQ_PC_READ_L; // loads address
|
case (dec_o_p1_optype)
|
if (op_JSR) next_state <= `SEQ_JSR_PUSH;
|
`OP_JSR: next_state <= `SEQ_JSR_PUSH;
|
else if (op_JMP) next_state <= `SEQ_JMP_LOAD_PC;
|
`OP_JMP: next_state <= `SEQ_JMP_LOAD_PC;
|
else
|
default:
|
|
begin
|
begin
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
(dec_o_left_path_addr == `RN_MEM8))
|
(dec_o_left_path_addr == `RN_MEM8))
|
begin
|
begin
|
| Line 588... |
Line 600... |
end
|
end
|
else
|
else
|
next_state <= `SEQ_GRAL_ALU; // no read
|
next_state <= `SEQ_GRAL_ALU; // no read
|
k_eahi <= regs_o_dp;
|
k_eahi <= regs_o_dp;
|
end
|
end
|
endcase
|
|
end
|
end
|
`INDEXED:
|
`INDEXED:
|
state <= `SEQ_IND_READ_EA;
|
state <= `SEQ_IND_READ_EA;
|
`EXTENDED:
|
`EXTENDED:
|
begin
|
begin
|
state <= `SEQ_PC_READ_H; // loads address
|
state <= `SEQ_PC_READ_H; // loads address
|
case (dec_o_p1_optype)
|
if (op_JSR) next_state <= `SEQ_JSR_PUSH;
|
`OP_JSR: next_state <= `SEQ_JSR_PUSH;
|
else if (op_JMP) next_state <= `SEQ_JMP_LOAD_PC;
|
`OP_JMP: next_state <= `SEQ_JMP_LOAD_PC;
|
else
|
default:
|
|
begin
|
begin
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
(dec_o_left_path_addr == `RN_MEM8))
|
(dec_o_left_path_addr == `RN_MEM8))
|
begin
|
begin
|
| Line 610... |
Line 620... |
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
end
|
end
|
else
|
else
|
next_state <= `SEQ_GRAL_ALU; // no read
|
next_state <= `SEQ_GRAL_ALU; // no read
|
end
|
end
|
endcase
|
|
end
|
end
|
`REL8:
|
`REL8:
|
begin
|
begin
|
state <= `SEQ_PC_READ_L; // loads address
|
state <= `SEQ_PC_READ_L; // loads address
|
if (dec_o_p1_optype == `OP_JSR) // bsr
|
if (op_JSR) // bsr
|
next_state <= `SEQ_JSR_PUSH;
|
next_state <= `SEQ_JSR_PUSH;
|
else
|
else
|
next_state <= `SEQ_JMP_LOAD_PC; // offset loaded in this cycle, jump if needed
|
next_state <= `SEQ_JMP_LOAD_PC; // offset loaded in this cycle, jump if needed
|
end
|
end
|
`REL16:
|
`REL16:
|
begin
|
begin
|
state <= `SEQ_PC_READ_H; // loads address
|
state <= `SEQ_PC_READ_H; // loads address
|
if (dec_o_p1_optype == `OP_JSR) // lbsr
|
if (op_JSR) // lbsr
|
next_state <= `SEQ_JSR_PUSH;
|
next_state <= `SEQ_JSR_PUSH;
|
else
|
else
|
next_state <= `SEQ_JMP_LOAD_PC;
|
next_state <= `SEQ_JMP_LOAD_PC;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
`SEQ_DECODE_P23:
|
`SEQ_DECODE_P23:
|
begin // has prefix 10 or 11
|
begin // has prefix 10 or 11
|
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`NONE: // unknown k_opcode... re-fetch ?
|
`NONE: // unknown k_opcode... re-fetch ?
|
|
if (op_EXG) begin k_write_exg <= 1; state <= `SEQ_TFREXG; end
|
|
else if (op_TFR) begin k_write_tfr <= 1; state <= `SEQ_TFREXG; end
|
|
else
|
state <= `SEQ_FETCH;
|
state <= `SEQ_FETCH;
|
`IMMEDIATE: // 8 or 16 bits as result decides..
|
`IMMEDIATE: // 8 or 16 bits as result decides..
|
begin
|
begin
|
case (k_opcode)
|
|
8'h1e: begin k_write_exg <= 1; state <= `SEQ_TFREXG; end
|
|
8'h1f: begin k_write_tfr <= 1; state <= `SEQ_TFREXG; end
|
|
default:
|
|
begin
|
|
next_state <= `SEQ_GRAL_ALU;
|
next_state <= `SEQ_GRAL_ALU;
|
if (dec_o_alu_size)
|
if (dec_o_alu_size)
|
state <= `SEQ_PC_READ_H;
|
state <= `SEQ_PC_READ_H;
|
else
|
else
|
state <= `SEQ_PC_READ_L;
|
state <= `SEQ_PC_READ_L;
|
end
|
end
|
endcase
|
|
end
|
|
`INHERENT:
|
`INHERENT:
|
case (k_opcode)
|
if (op_SWI) state <= (k_p2_valid) ? `SEQ_SWI2:`SEQ_SWI3;
|
8'h3f: if (k_p2_valid) state <= `SEQ_SWI2;
|
else state <= `SEQ_GRAL_ALU;
|
else state <= `SEQ_SWI3;
|
|
default: state <= `SEQ_GRAL_ALU;
|
|
endcase
|
|
`DIRECT:
|
`DIRECT:
|
begin
|
begin
|
state <= `SEQ_PC_READ_L;
|
state <= `SEQ_PC_READ_L;
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
| Line 704... |
Line 706... |
k_mul_cnt <= 1'h0;
|
k_mul_cnt <= 1'h0;
|
end
|
end
|
`SEQ_GRAL_WBACK:
|
`SEQ_GRAL_WBACK:
|
begin
|
begin
|
next_mem_state <= `SEQ_FETCH;
|
next_mem_state <= `SEQ_FETCH;
|
casex (k_opcode)
|
if (op_CWAI) state <= `SEQ_CWAI_STACK; // CWAI
|
8'h3C: state <= `SEQ_CWAI_STACK; // CWAI
|
else
|
default:
|
|
case (dec_o_dest_reg_addr)
|
case (dec_o_dest_reg_addr)
|
`RN_MEM8: state <= `SEQ_MEM_WRITE_L;
|
`RN_MEM8: state <= `SEQ_MEM_WRITE_L;
|
`RN_MEM16: state <= `SEQ_MEM_WRITE_H;
|
`RN_MEM16: state <= `SEQ_MEM_WRITE_H;
|
default:
|
default:
|
begin
|
begin
|
state <= `SEQ_FETCH;
|
state <= `SEQ_FETCH;
|
k_write_post_incdec <= dec_o_ea_wpost & (dec_o_p1_mode == `INDEXED);
|
k_write_post_incdec <= dec_o_ea_wpost & (dec_o_p1_mode == `INDEXED);
|
end
|
end
|
endcase
|
endcase
|
endcase
|
|
end
|
end
|
`SEQ_CWAI_STACK:
|
`SEQ_CWAI_STACK:
|
begin
|
begin
|
k_pp_regs <= 8'hff;
|
k_pp_regs <= 8'hff;
|
k_set_e <= 1;
|
k_set_e <= 1;
|
| Line 830... |
Line 830... |
begin // load 2 bytes offset
|
begin // load 2 bytes offset
|
state <= `SEQ_PC_READ_H;
|
state <= `SEQ_PC_READ_H;
|
next_state <= `SEQ_IND_DECODE_OFS; // has some offset, load arg
|
next_state <= `SEQ_IND_DECODE_OFS; // has some offset, load arg
|
end
|
end
|
else
|
else
|
if (dec_o_p1_optype == `OP_JSR) // jsr
|
if (op_JSR) // jsr
|
begin
|
|
next_state <= `SEQ_JSR_PUSH;
|
next_state <= `SEQ_JSR_PUSH;
|
end
|
|
else
|
else
|
begin // no extra load...
|
begin // no extra load...
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
(dec_o_left_path_addr == `RN_MEM8))
|
(dec_o_left_path_addr == `RN_MEM8))
|
begin
|
begin
|
| Line 851... |
Line 849... |
state <= `SEQ_GRAL_ALU; // no load, then store
|
state <= `SEQ_GRAL_ALU; // no load, then store
|
end
|
end
|
end
|
end
|
`SEQ_IND_DECODE_OFS: // loads argument if needed
|
`SEQ_IND_DECODE_OFS: // loads argument if needed
|
begin
|
begin
|
if (dec_o_p1_optype == `OP_JSR) // jsr
|
if (op_JSR) // jsr
|
begin
|
|
next_state <= `SEQ_JSR_PUSH;
|
next_state <= `SEQ_JSR_PUSH;
|
end
|
|
else
|
else
|
begin
|
begin
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
(dec_o_left_path_addr == `RN_MEM8))
|
(dec_o_left_path_addr == `RN_MEM8))
|
begin
|
begin
|
| Line 916... |
Line 912... |
end
|
end
|
else
|
else
|
state <= `SEQ_FETCH; // end of sequence
|
state <= `SEQ_FETCH; // end of sequence
|
if (k_pp_regs[0]) begin k_pp_active_reg <= `RN_CC; k_pp_regs[0] <= 0; state <= `SEQ_MEM_READ_L; end
|
if (k_pp_regs[0]) begin k_pp_active_reg <= `RN_CC; k_pp_regs[0] <= 0; state <= `SEQ_MEM_READ_L; end
|
else
|
else
|
if ((k_opcode == 8'h3B) && (!`FLAGE)) // not all registers have to be pulled
|
if (op_RTI && (!`FLAGE)) // not all registers have to be pulled
|
begin
|
begin
|
k_pp_active_reg <= `RN_PC; k_pp_regs <= 0; state <= `SEQ_MEM_READ_H;
|
k_pp_active_reg <= `RN_PC; k_pp_regs <= 0; state <= `SEQ_MEM_READ_H;
|
end
|
end
|
else
|
else
|
if (k_pp_regs[1]) begin k_pp_active_reg <= `RN_ACCA; k_pp_regs[1] <= 0; state <= `SEQ_MEM_READ_L; end
|
if (k_pp_regs[1]) begin k_pp_active_reg <= `RN_ACCA; k_pp_regs[1] <= 0; state <= `SEQ_MEM_READ_L; end
|
| Line 1015... |
Line 1011... |
state <= next_state;
|
state <= next_state;
|
end
|
end
|
`SEQ_MEM_READ_H: // reads high byte
|
`SEQ_MEM_READ_H: // reads high byte
|
begin
|
begin
|
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`NONE: begin k_cpu_addr <= regs_o_su; k_inc_su <= 1; end // pull, rts, rti
|
|
`INDEXED:
|
`INDEXED:
|
if (k_indirect_loaded)
|
if (k_indirect_loaded)
|
k_cpu_addr <= { k_memhi, k_memlo };
|
k_cpu_addr <= { k_memhi, k_memlo };
|
else
|
else
|
k_cpu_addr <= regs_o_eamem_addr;
|
k_cpu_addr <= regs_o_eamem_addr;
|
default: k_cpu_addr <= { k_eahi, k_ealo };
|
default:
|
|
if (op_PULL | op_RTI | op_RTS)
|
|
begin
|
|
k_cpu_addr <= regs_o_su;
|
|
k_inc_su <= 1;
|
|
end
|
|
else
|
|
k_cpu_addr <= { k_eahi, k_ealo };
|
endcase
|
endcase
|
if (k_forced_mem_size | dec_o_source_size | (k_pp_active_reg < `RN_ACCA))
|
if (k_forced_mem_size | dec_o_source_size | (k_pp_active_reg < `RN_ACCA))
|
state <= `SEQ_MEM_READ_H_1;
|
state <= `SEQ_MEM_READ_H_1;
|
else
|
else
|
state <= `SEQ_MEM_READ_L_1;
|
state <= `SEQ_MEM_READ_L_1;
|
| Line 1043... |
Line 1045... |
`MEMDEST_MH: k_memhi <= cpu_data_i;
|
`MEMDEST_MH: k_memhi <= cpu_data_i;
|
`MEMDEST_AH: k_eahi <= cpu_data_i;
|
`MEMDEST_AH: k_eahi <= cpu_data_i;
|
endcase
|
endcase
|
state <= `SEQ_MEM_READ_L_1;
|
state <= `SEQ_MEM_READ_L_1;
|
k_cpu_addr <= k_cpu_addr + 16'h1;
|
k_cpu_addr <= k_cpu_addr + 16'h1;
|
case (dec_o_p1_mode)
|
if (op_PULL | op_RTI | op_RTS)
|
`NONE: begin k_inc_su <= 1; end // pull, rts, rti
|
k_inc_su <= 1;
|
endcase
|
|
end
|
end
|
`SEQ_MEM_READ_L: // reads low byte
|
`SEQ_MEM_READ_L: // reads low byte
|
begin
|
begin
|
// falls through from READ_MEM_H with the right address
|
// falls through from READ_MEM_H with the right address
|
case (dec_o_p1_mode)
|
if (op_PULL | op_RTI | op_RTS)
|
`NONE: begin k_cpu_addr <= regs_o_su; k_inc_su <= 1; end // pull, rts, rti
|
begin
|
endcase
|
k_cpu_addr <= regs_o_su;
|
|
k_inc_su <= 1;
|
|
end
|
state <= `SEQ_MEM_READ_L_1;
|
state <= `SEQ_MEM_READ_L_1;
|
end
|
end
|
`SEQ_MEM_READ_L_1:
|
`SEQ_MEM_READ_L_1:
|
begin
|
begin
|
k_cpu_oe <= 1; // read
|
k_cpu_oe <= 1; // read
|
| Line 1067... |
Line 1070... |
case (k_mem_dest)
|
case (k_mem_dest)
|
`MEMDEST_PC,
|
`MEMDEST_PC,
|
`MEMDEST_MH: k_memlo <= cpu_data_i;
|
`MEMDEST_MH: k_memlo <= cpu_data_i;
|
`MEMDEST_AH: k_ealo <= cpu_data_i;
|
`MEMDEST_AH: k_ealo <= cpu_data_i;
|
endcase
|
endcase
|
case (dec_o_p1_mode)
|
if (op_PULL | op_RTI | op_RTS) k_write_dest <= 1; // FIXME: which other opcode is inherent and needs write-back ?
|
`NONE, `INHERENT: k_write_dest <= 1; // pull, rts, rti
|
|
endcase
|
|
if (next_mem_state == `SEQ_LOADPC)
|
if (next_mem_state == `SEQ_LOADPC)
|
k_write_pc <= 1;
|
k_write_pc <= 1;
|
case (dec_o_p1_mode)
|
case (dec_o_p1_mode)
|
`INDEXED: // address loaded, load argument
|
`INDEXED: // address loaded, load argument
|
if (k_indirect_loaded | (!dec_o_ea_indirect))
|
if (k_indirect_loaded | (!dec_o_ea_indirect))
|
