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Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [alu16.v] - Diff between revs 10 and 12

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Rev 10 Rev 12
Line 24... Line 24... 
        );
 
        );
 
 
 
 
 
wire [7:0] ccr8_out, q8_out;
 
wire [7:0] ccr8_out, q8_out;
 
wire [15:0] q16_out;
 
wire [15:0] q16_out;
 
wire [3:0] ccr16_out;
 
wire [3:0] ccr16_out;
 
 
 
wire [15:0] q16_mul;
 
reg [15:0] ra_in, rb_in;
 
reg [15:0] ra_in, rb_in;
 
reg [4:0] rop_in;
 
reg [4:0] rop_in;
 
 
 
 
 
 
 
 
 
 
 
mul8x8 mulu(clk_in, a_in[7:0], b_in[7:0], q16_mul);
 
alu8 alu8(clk_in, ra_in[7:0], rb_in[7:0], CCR, rop_in, q8_out, ccr8_out);
 
alu8 alu8(clk_in, ra_in[7:0], rb_in[7:0], CCR, rop_in, q8_out, ccr8_out);
 
alu16 alu16(clk_in, ra_in, rb_in, CCR, rop_in, q16_out, ccr16_out);
 
alu16 alu16(clk_in, ra_in, rb_in, CCR, rop_in, q16_mul, q16_out, ccr16_out);
 
 
 
 
 
 
 
 
 
always @(posedge clk_in)
 
always @(posedge clk_in)
 
        begin
 
        begin
 
                ra_in <= a_in;
 
                ra_in <= a_in;
 
                rb_in <= b_in;
 
                rb_in <= b_in;
Line 114... Line 118... 
        end
 
        end
 
 
 
 
 
always @(*)
 
always @(*)
 
        begin
 
        begin
 
                case (opcode_in[0])
 
                case (opcode_in[0])
 
                        1'b0: half_c_out = (a_in[3] & b_in[3] & (~q_out[3])) | ((~a_in[3]) & (~b_in[3]) & q_out[3]);
 
                        1'b0: half_c_out = (a_in[4] ^ b_in[4] ^ q_out[4]);
 
                        1'b1: half_c_out = half_c_in;
 
                        1'b1: half_c_out = half_c_in;
 
                endcase
 
                endcase
 
        end
 
        end
 
 
 
 
 
endmodule
 
endmodule
Line 189... Line 193... 
                        3'b011: overflow_out = a_in[7] ^ a_in[6]; // ROL
 
                        3'b011: overflow_out = a_in[7] ^ a_in[6]; // ROL
 
                        3'b100: overflow_out = overflow_in; // ASR
 
                        3'b100: overflow_out = overflow_in; // ASR
 
                endcase
 
                endcase
 
        end
 
        end
 
 
 
 
 
assign carry_out = opcode_in[0] ? a_in[0]:a_in[7];
 
assign carry_out = opcode_in[0] ? a_in[7]:a_in[0];
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
 
 
module alu8(
 
module alu8(
Line 211... Line 215... 
assign n_in = CCR[3]; /* neg flag */
 
assign n_in = CCR[3]; /* neg flag */
 
assign v_in = CCR[1]; /* overflow flag */
 
assign v_in = CCR[1]; /* overflow flag */
 
assign z_in = CCR[2]; /* zero flag */
 
assign z_in = CCR[2]; /* zero flag */
 
assign h_in = CCR[5]; /* halb-carry flag */
 
assign h_in = CCR[5]; /* halb-carry flag */
 
 
 
 
 
wire [7:0] com8_r, neg8_r;
 
wire [7:0] com8_r, neg8_r, daa_p0_r;
 
wire [3:0] daa8l_r, daa8h_r;
 
wire [3:0] daa8h_r;
 
wire daa_lnm9;
 
 
 
 
 
 
 
wire [7:0] com8_w, neg8_w;
 
wire [7:0] com8_w, neg8_w;
 
 
 
 
 
wire ccom8_r, cneg8_r, cdaa8_r;
 
wire ccom8_r, cneg8_r, cdaa8_r;
 
 
 
 
Line 231... Line 234... 
assign vcom8_r = 1'b0;
 
assign vcom8_r = 1'b0;
 
                // NEG
 
                // NEG
 
assign neg8_r = neg8_w;
 
assign neg8_r = neg8_w;
 
assign cneg8_r = neg8_w[7] | neg8_w[6] | neg8_w[5] | neg8_w[4] | neg8_w[3] | neg8_w[2] | neg8_w[1] | neg8_w[0];
 
assign cneg8_r = neg8_w[7] | neg8_w[6] | neg8_w[5] | neg8_w[4] | neg8_w[3] | neg8_w[2] | neg8_w[1] | neg8_w[0];
 
assign vneg8_r = neg8_w[7] & (~neg8_w[6]) & (~neg8_w[5]) & (~neg8_w[4]) & (~neg8_w[3]) & (~neg8_w[2]) & (~neg8_w[1]) & (~neg8_w[0]);
 
assign vneg8_r = neg8_w[7] & (~neg8_w[6]) & (~neg8_w[5]) & (~neg8_w[4]) & (~neg8_w[3]) & (~neg8_w[2]) & (~neg8_w[1]) & (~neg8_w[0]);
 
                // DAA
 
 
 
assign daa_lnm9 = (a_in[3:0] > 9);
 
 
 
assign daa8l_r = (daa_lnm9 | h_in ) ? a_in[3:0] + 4'h6:a_in[3:0];
 
 
 
assign daa8h_r = ((a_in[7:4] > 9) || (c_in == 1'b1) || (a_in[7] & daa_lnm9)) ? a_in[7:4] + 4'h6:a_in[7:4];
 
 
 
assign cdaa8_r = daa8h_r < a_in[7:4];
 
 
 
 
 
 
 
reg c8, h8, n8, v8, z8;
 
reg c8, h8, n8, v8, z8;
 
reg [7:0] q8;
 
reg [7:0] q8;
 
 
 
 
 
wire [7:0] logic_q, arith_q, shift_q;
 
wire [7:0] logic_q, arith_q, shift_q;
Line 247... Line 245... 
wire shift_c, shift_v;
 
wire shift_c, shift_v;
 
 
 
 
 
logic8 l8(a_in, b_in, opcode_in[1:0], logic_q);
 
logic8 l8(a_in, b_in, opcode_in[1:0], logic_q);
 
arith8 a8(a_in, b_in, c_in, h_in, opcode_in[1:0], arith_q, arith_c, arith_v, arith_h);
 
arith8 a8(a_in, b_in, c_in, h_in, opcode_in[1:0], arith_q, arith_c, arith_v, arith_h);
 
shift8 s8(a_in, b_in, c_in, v_in, opcode_in[2:0], shift_q, shift_c, shift_v);
 
shift8 s8(a_in, b_in, c_in, v_in, opcode_in[2:0], shift_q, shift_c, shift_v);
 
 
 
                // DAA
 
 
 
assign daa_p0_r = ((a_in[3:0] > 4'h9) | h_in ) ? a_in[7:0] + 8'h6:a_in[7:0];
 
 
 
assign { cdaa8_r, daa8h_r } = ((daa_p0_r[7:4] > 9) || (c_in == 1'b1)) ? { 1'b0, daa_p0_r[7:4] } + 5'h6:{ 1'b0, daa_p0_r[7:4] };
 
 
 
 
 
always @(*)
 
always @(*)
 
        begin
 
        begin
 
                q8 = 8'h0;
 
                q8 = 8'h0;
 
                c8 = c_in;
 
                c8 = c_in;
 
                h8 = h_in;
 
                h8 = h_in;
 
                v8 = v_in;
 
                v8 = v_in;
 
                case (opcode_in)
 
                case (opcode_in)
 
 
 
                        `SEXT:
 
 
 
                                begin
 
 
 
                                        q8 = a_in[7] ? 8'hff:8'h00;
 
 
 
                                end
 
                        `ADD, `ADC, `SUB, `SBC:
 
                        `ADD, `ADC, `SUB, `SBC:
 
                                begin
 
                                begin
 
                                        q8 = arith_q;
 
                                        q8 = arith_q;
 
                                        c8 = arith_c;
 
                                        c8 = arith_c;
 
                                        v8 = arith_v;
 
                                        v8 = arith_v;
 
                                        h8 = arith_h;
 
                                        h8 = arith_h;
 
                                end
 
                                end
 
 
 
                        `DEC, `INC:
 
 
 
                                begin
 
 
 
                                        q8 = arith_q;
 
 
 
                                        v8 = arith_v;
 
 
 
                                end
 
                        `COM:
 
                        `COM:
 
                                begin
 
                                begin
 
                                        q8 = com8_r;
 
                                        q8 = com8_r;
 
                                        c8 = com8_r;
 
                                        c8 = com8_r;
 
                                        v8 = vcom8_r;
 
                                        v8 = vcom8_r;
Line 287... Line 297... 
                                        q8 = logic_q;
 
                                        q8 = logic_q;
 
                                        v8 = 1'b0;
 
                                        v8 = 1'b0;
 
                                        end
 
                                        end
 
                        `DAA:
 
                        `DAA:
 
                                begin // V is undefined, so we don't touch it
 
                                begin // V is undefined, so we don't touch it
 
                                        q8 = { daa8h_r, daa8l_r };
 
                                        q8 = { daa8h_r, daa_p0_r[3:0] };
 
                                        c8 = cdaa8_r;
 
                                        c8 = cdaa8_r;
 
                                end
 
                                end
 
                        `ST:
 
                        `ST:
 
                                begin
 
                                begin
 
                                        q8 = a_in[7:0];
 
                                        q8 = a_in[7:0];
 
                                end
 
                                end
 
                endcase
 
                endcase
 
        end
 
        end
 
 
 
/*
 
reg [7:0] regq8;
 
reg [7:0] regq8;
 
/* register before second mux */
 
// register before second mux
 
always @(posedge clk_in)
 
always @(posedge clk_in)
 
        begin
 
        begin
 
                regq8 <= q8;
 
                regq8 <= q8;
 
        end
 
        end
 
 
 
*/
 
always @(*)
 
always @(*)
 
        begin
 
        begin
 
                q_out[7:0] = q8; //regq8;
 
                q_out[7:0] = q8; //regq8;
 
                case (opcode_in)
 
                CCRo = { CCR[7:6], h8, CCR[4], q8[7], (q8 == 8'h0), v8, c8 };
 
                        `ORCC:
 
 
 
                                CCRo = CCR | b_in[7:0];
 
 
 
                        `ANDCC:
 
 
 
                                CCRo = CCR & b_in[7:0];
 
 
 
                        default:
 
 
 
                                CCRo = { CCR[7:6], CCR[5], h8, q8[7], (q8 == 8'h0), v8, c8 };
 
 
 
                endcase
 
 
 
        end
 
        end
 
 
 
 
 
initial
 
initial
 
        begin
 
        begin
 
        end
 
        end
Line 329... Line 332... 
        input wire clk_in,
 
        input wire clk_in,
 
        input wire [15:0] a_in,
 
        input wire [15:0] a_in,
 
        input wire [15:0] b_in,
 
        input wire [15:0] b_in,
 
        input wire [7:0] CCR, /* condition code register */
 
        input wire [7:0] CCR, /* condition code register */
 
        input wire [4:0] opcode_in, /* ALU opcode */
 
        input wire [4:0] opcode_in, /* ALU opcode */
 
 
 
        input wire [15:0] q_mul_in,
 
        output reg [15:0] q_out, /* ALU result */
 
        output reg [15:0] q_out, /* ALU result */
 
        output reg [3:0] CCRo
 
        output reg [3:0] CCRo
 
        );
 
        );
 
 
 
 
 
wire c_in, n_in, v_in, z_in;
 
wire c_in, n_in, v_in, z_in;
Line 401... Line 405... 
assign or16_r = or16_w;
 
assign or16_r = or16_w;
 
                // EOR
 
                // EOR
 
assign eor16_r = eor16_w;
 
assign eor16_r = eor16_w;
 
`endif
 
`endif
 
 
 
 
 
wire [15:0] q16_mul;
 
 
 
 
 
 
 
mul8x8 mulu(clk_in, a_in[7:0], b_in[7:0], q16_mul);
 
 
 
 
 
 
 
reg c16, n16, v16, z16;
 
reg c16, n16, v16, z16;
 
reg [15:0] q16;
 
reg [15:0] q16;
 
 
 
 
 
wire [15:0] arith_q;
 
wire [15:0] arith_q;
 
wire arith_c, arith_v, arith_h;
 
wire arith_c, arith_v, arith_h;
Line 489... Line 489... 
                                        v16 = vand16_r;
 
                                        v16 = vand16_r;
 
                                end
 
                                end
 
`endif
 
`endif
 
                        `MUL:
 
                        `MUL:
 
                                begin
 
                                begin
 
                                        q16 = q16_mul;
 
                                        q16 = q_mul_in;
 
                                        c16 = q16_mul[7];
 
                                        c16 = q_mul_in[7];
 
                                end
 
                                end
 
                        `LD:
 
                        `LD:
 
                                begin
 
                                begin
 
                                        v16 = 0;
 
                                        v16 = 0;
 
                                        q16 = b_in[15:0];
 
                                        q16 = b_in[15:0];

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