| Line 4... |
Line 4... |
*
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*
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*
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*
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*
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*
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*/
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*/
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`include "defs.v"
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`include "defs.v"
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module decode_regs(
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input wire cpu_clk,
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module decoders(
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input wire clk_in,
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input wire [7:0] opcode,
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input wire [7:0] opcode,
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input wire [7:0] postbyte0,
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input wire [7:0] postbyte0,
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input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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output wire [3:0] path_left_addr_o,
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output wire [3:0] path_left_addr_o,
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output wire [3:0] path_right_addr_o,
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output wire [3:0] path_right_addr_o,
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output wire [3:0] dest_reg_o,
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output wire [3:0] dest_reg_o,
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output reg [3:0] path_left_addr_lo,
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output reg [3:0] path_left_addr_lo,
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output reg [3:0] path_right_addr_lo,
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output reg [3:0] path_right_addr_lo,
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output reg [3:0] dest_reg_lo,
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output reg [3:0] dest_reg_lo,
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output wire write_dest,
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output wire write_dest,
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output wire source_size,
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output wire source_size,
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output wire result_size
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output wire result_size,
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);
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output wire [1:0] path_left_memtype_o,
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reg [3:0] path_left_addr, path_right_addr, dest_reg;
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output wire [1:0] path_right_memtype_o,
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// for registers, memory writes are handled differently
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output wire [1:0] dest_memtype_o,
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assign write_dest = (dest_reg != `RN_INV);
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output reg [1:0] path_left_memtype_lo,
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assign source_size = (path_left_addr < `RN_ACCA);
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output reg [1:0] path_right_memtype_lo,
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// result size is used to determine the size of the argument
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output reg [1:0] dest_memtype_lo,
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// to load, compare has no result, thus the source is used instead,
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output wire operand_read_o, // reads 1 operand from memory
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// why do we need the result size ?... because of tfr&exg
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output wire operand_write_o, // writes result to memory
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assign result_size = (dest_reg == `RN_INV) ? (path_left_addr < `RN_ACCA):
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(dest_reg < `RN_IMM16) ? 1:0;
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assign path_right_addr_o = path_right_addr;
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output wire [2:0] mode,
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assign path_left_addr_o = path_left_addr;
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assign dest_reg_o = dest_reg;
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always @(opcode, postbyte0, page2_valid, page3_valid)
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begin
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path_left_addr = `RN_INV;
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path_right_addr = `RN_INV;
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dest_reg = `RN_INV;
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if (page2_valid)
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begin
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casex(postbyte0)
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8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_ACCD; // cmpd
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8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_IY; // cmpy
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8'h8e, 8'h9e, 8'hae, 8'hbe: path_left_addr = `RN_IY; // ldy
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8'h8f, 8'h9f, 8'haf, 8'hbf: path_left_addr = `RN_IY; // sty
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8'hdf, 8'hef, 8'hff: path_left_addr = `RN_S; // STS
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endcase
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casex (postbyte0) // right arm
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8'h83, 8'h8c, 8'h8e, 8'hce: path_right_addr = `RN_IMM16;
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8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16;
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8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16;
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8'h9e, 8'hae, 8'hbe: path_right_addr = `RN_MEM16;
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8'h9f, 8'haf, 8'hbf: path_right_addr = `RN_MEM16; // STY
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8'hde, 8'hee, 8'hfe: path_right_addr = `RN_MEM16; // lds
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endcase
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casex(postbyte0) // dest
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8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpd
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8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmpy
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8'h8e, 8'h9e, 8'hae, 8'hbe: dest_reg = `RN_IY; // LDY
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8'hce, 8'hde, 8'hee, 8'hfe: dest_reg = `RN_S; // LDS
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8'h9f, 8'haf, 8'hbf: dest_reg = `RN_MEM16; // STY
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8'hdf, 8'hef, 8'hff: dest_reg = `RN_MEM16; // STS
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endcase
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end
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if (page3_valid)
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begin
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casex(postbyte0)
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8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_U; // CMPU
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8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_S; // CMPS
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endcase
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casex (postbyte0) // right arm
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8'h83, 8'h8c: path_right_addr = `RN_IMM16; // CMPU, CMPS
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8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16; // CMPU
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8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16; // CMPS
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endcase
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casex(postbyte0) // dest
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8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpu
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8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmps
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endcase
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end
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// destination
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casex(opcode)
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8'h1a, 8'h1c: begin path_left_addr = `RN_CC; path_right_addr = `RN_IMM8; dest_reg = `RN_CC; end // ANDCC, ORCC
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8'h19: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end // DAA
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8'h1d: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCA; end // SEX
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8'h1e, 8'h1f: begin dest_reg = postbyte0[3:0]; path_left_addr = postbyte0[7:4]; path_right_addr = postbyte0[3:0]; end // tfr, exg
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8'h30: dest_reg = `RN_IX;
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8'h31: dest_reg = `RN_IY;
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8'h32: dest_reg = `RN_S;
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8'h33: dest_reg = `RN_U;
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8'h39: dest_reg = `RN_PC; // rts
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8'h3d: begin path_left_addr = `RN_ACCA; path_right_addr = `RN_ACCB; dest_reg = `RN_ACCD; end // mul
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8'h4x: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
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8'h5x: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
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8'h0x, 8'h6x, 8'h7x:
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case (opcode[3:0])
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4'he: begin end // no source or dest for jmp
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4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
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default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
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endcase
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8'h8x, 8'h9x, 8'hax, 8'hbx:
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case (opcode[3:0]) // default A->A
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4'h1, 4'h5: path_left_addr = `RN_ACCA; // CMP, BIT
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4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
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4'h7: begin path_left_addr = `RN_ACCA; dest_reg = `RN_MEM8; end // sta
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4'hc: path_left_addr = `RN_IX; // cmpx
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4'hd: begin end // nothing active, jsr
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4'he: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end // ldx
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4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_MEM16; end // stx
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default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
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endcase
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8'hcx, 8'hdx, 8'hex, 8'hfx:
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case (opcode[3:0])
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4'h1, 4'h5: path_left_addr = `RN_ACCB; // CMP, BIT
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4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end // addd
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4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // stb
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4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end // ldd
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4'hd: begin path_left_addr = `RN_ACCD; dest_reg = `RN_MEM16; end // STD
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4'he: begin dest_reg = `RN_U; end // LDU
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4'hf: begin path_left_addr = `RN_U; dest_reg = `RN_MEM16; end // STU
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default: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
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endcase
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endcase
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casex (opcode) // right arm
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// 8x and Cx
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8'b1x00_000x, 8'b1x00_0010, // sub, cmp, scb
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8'b1x00_010x, 8'b1x00_0110, 8'b1x00_10xx: path_right_addr = `RN_IMM8;
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// 83, C3, 8C, CC, 8E, CE
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8'b1x00_0011, 8'b1x00_11x0: path_right_addr = `RN_IMM16; // cmpd, cmpx, ldx
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// 9, A, B, D, E, F
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8'b1x01_000x, 8'b1x01_0010, // x0, x1, x2: sub cmp, scb
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8'b1x01_010x, 8'b1x01_0110, 8'b1x01_10xx,
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8'b1x1x_000x, 8'b1x1x_0010,
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8'b1x1x_010x, 8'b1x1x_0110, 8'b1x1x_10xx: path_right_addr = `RN_MEM8;
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// 9x, Ax, Bx, Dx, Ex, Fx
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8'h93, 8'ha3, 8'hb3, // subd
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8'hd3, 8'he3, 8'hf3, // addd
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8'h9c, 8'hac, 8'hbc, // cmpx
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8'hdc, 8'hec, 8'hfc, // ldd
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//8'hdd, 8'hed, 8'hfd, // std
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8'h9e, 8'hae, 8'hbe, // ldx
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8'hde, 8'hee, 8'hfe, // ldu
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//8'h9f, 8'haf, 8'hbf, // stx
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8'hdf, 8'hef, 8'hff: path_right_addr = `RN_MEM16;// stu
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endcase
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end
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// latched versions are used to fetch regsiters
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// not-latched version in the decoder
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always @(posedge cpu_clk)
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begin
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path_right_addr_lo <= path_right_addr;
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path_left_addr_lo <= path_left_addr;
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dest_reg_lo <= dest_reg;
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end
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endmodule
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/* Decodes module and addressing mode for page 1 opcodes */
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module decode_op(
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input wire [7:0] opcode,
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input wire [7:0] postbyte0,
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input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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output reg [2:0] mode,
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output reg [2:0] optype,
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output reg op_SYNC,
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output reg op_SYNC,
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output reg op_EXG,
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output reg op_EXG,
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output reg op_TFR,
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output reg op_TFR,
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output reg op_RTS,
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output reg op_RTS,
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output reg op_RTI,
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output reg op_RTI,
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| Line 180... |
Line 44... |
output reg op_PUSH,
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output reg op_PUSH,
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output reg op_PULL,
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output reg op_PULL,
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output reg op_LEA,
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output reg op_LEA,
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output reg op_JMP,
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output reg op_JMP,
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output reg op_JSR,
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output reg op_JSR,
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output reg use_s
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output wire use_s,
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output wire [4:0] alu_opcode,
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output wire dest_flags_o
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);
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);
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reg [3:0] lr, rr, dr;
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reg [1:0] lm, rm, dm;
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reg ss, sz, p2, p3;
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reg [2:0] mo;
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reg [4:0] aop;
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assign write_dest = (dr != `RN_INV);
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assign source_size = (lr < `RN_ACCA) | sz | (rm == `MT_WORD);
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// result size is used to determine the size of the argument
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// to load, compare has no result, thus the source is used instead,
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// why do we need the result size ?... because of tfr&exg
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assign result_size = (dr == `RN_INV) ? (lr < `RN_ACCA):
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(dr < `RN_ACCA) ? 1:0;
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assign path_right_addr_o = rr;
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assign path_left_addr_o = lr;
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assign dest_reg_o = dr;
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// for registers, memory writes are handled differently
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assign operand_read_o = (lm != `MT_NONE) | (rm != `MT_NONE);
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assign operand_write_o = dm != `MT_NONE;
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assign path_left_memtype_o = lm;
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assign path_right_memtype_o = rm;
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assign dest_memtype_o = dm;
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assign dest_flags_o = (aop != `NOP) && (opcode != 8'h1a) && (opcode != 8'h1c);
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assign use_s = ss;
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assign mode = mo;
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assign alu_opcode = aop;
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wire [3:0] oplo;
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always @(*)
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reg size;
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begin
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assign oplo = opcode[3:0];
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lr = `RN_INV;
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rr = `RN_INV;
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always @(opcode, postbyte0, page2_valid, page3_valid, oplo)
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dr = `RN_INV;
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begin
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lm = `MT_NONE;
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//dsize = `DSZ_8; // data operand size
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rm = `MT_NONE;
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//msize = `MSZ_8; // memory operand size
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dm = `MT_NONE;
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use_s = 1;
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mo = `NONE;
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mode = `NONE;
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aop = `NOP;
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size = 0;
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ss = 1;
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sz = 0;
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op_SYNC = 0;
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op_SYNC = 0;
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op_EXG = 0;
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op_EXG = 0;
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op_TFR = 0;
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op_TFR = 0;
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op_RTS = 0;
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op_RTS = 0;
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op_RTI = 0;
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op_RTI = 0;
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| Line 207... |
Line 105... |
op_PUSH = 0;
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op_PUSH = 0;
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op_PULL = 0;
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op_PULL = 0;
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op_LEA = 0;
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op_LEA = 0;
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op_JMP = 0;
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op_JMP = 0;
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op_JSR = 0;
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op_JSR = 0;
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// Addressing mode
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p2 = 0;
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casex(opcode)
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p3 = 0;
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8'h0x: begin mode = `DIRECT; end
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case (opcode[7:4])
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//8'h0e: begin optype = `OP_JMP; end
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4'h0:
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8'h12, 8'h13, 8'h19: mode = `INHERENT;
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begin
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8'h14, 8'h15, 8'h18, 8'h1b: mode = `NONE; // undefined opcodes
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mo = `DIRECT;
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8'h16: mode = `REL16;
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lm = `MT_BYTE;
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8'h17: begin mode = `REL16; op_JSR = 1; end
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dm = `MT_BYTE;
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8'h1a, 8'h1c, 8'h1d: mode = `IMMEDIATE; // handled in ALU ORCC, ANDCC, SEX
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case (opcode[3:0]) // Direct
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8'h1e: op_EXG = 1;
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4'h0: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `NEG; end // NEG
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8'h1f: op_TFR = 1;
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4'h1: begin end
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8'h2x: mode = `REL8;
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4'h2: begin end
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8'h30, 8'h31, 8'h32, 8'h33: begin mode = `INDEXED; op_LEA = 1; end
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4'h3: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `COM; end // COM
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8'h34: op_PUSH = 1;
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4'h4: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `LSR; end
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8'h35: op_PULL = 1;
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4'h5: begin end
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8'h36: begin op_PUSH = 1; use_s = 0; end
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4'h6: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `ROR; end
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8'h37: begin op_PULL = 1; use_s = 0; end
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4'h7: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `ASR; end
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8'h38, 8'h3e: mode = `NONE;
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4'h8: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `LSL; end
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// don't change to inh because SEQ_MEM_READ_x would not use register S as address
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4'h9: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `ROL; end
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8'h39: begin op_RTS = 1; mode = `INHERENT; end
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4'ha: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `DEC; end
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8'h3b: begin op_RTI = 1; mode = `INHERENT; end
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4'hb: begin end
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8'h3a, 8'h3c: mode = `INHERENT;
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4'hc: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `INC; end
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8'h3d: begin op_MUL = 1; mode = `INHERENT; end
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4'hd: begin lm = `MT_BYTE; aop = `TST; end
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8'h3f: begin op_SWI = 1; mode = `INHERENT; end
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4'he: begin op_JMP = 1; end // JMP
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8'h4x: begin mode = `INHERENT; end
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4'hf: begin dm = `MT_BYTE; aop = `CLR; end
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8'h5x: begin mode = `INHERENT; end
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endcase
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8'h6x: begin mode = `INDEXED; end
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end
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//8'h6e: begin optype = `OP_JMP; end
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4'h1:
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8'h7x: begin mode = `EXTENDED; end
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begin
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//8'h7e: begin optype = `OP_JMP; end
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case (opcode[3:0])
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8'h8x:
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4'h0: begin p2 = 1; end
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begin
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4'h1: begin p3 = 1; end
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case (oplo)
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4'h2: begin end // nop
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4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
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4'h3: begin op_SYNC = 1; end
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4'hd: mode = `REL8; // bsr
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4'h4: begin end
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default: mode = `IMMEDIATE;
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4'h5: begin end
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endcase
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4'h6: begin mo = `REL16; end // lbra
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end
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4'h7: begin mo = `REL16; op_JSR = 1; end
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8'hcx:
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4'h8: begin end
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begin
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4'h9: begin mo = `INHERENT; lr = `RN_ACCA; dr = `RN_ACCA; aop = `DAA; end
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case (oplo)
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4'ha: begin mo = `IMMEDIATE; lr = `RN_CC; dr = `RN_CC; aop = `OR; end
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4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
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4'hb: begin end
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default: mode = `IMMEDIATE;
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4'hc: begin mo = `IMMEDIATE; lr = `RN_CC; dr = `RN_CC; aop = `AND; end
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endcase
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4'hd: begin mo = `INHERENT; lr = `RN_ACCB; dr = `RN_ACCA; aop = `SEXT; end
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end
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4'he: begin op_EXG = 1; lr = postbyte0[7:4]; rr = postbyte0[3:0]; dr = postbyte0[3:0]; end
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8'h9x, 8'hdx: begin mode = `DIRECT; end
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4'hf: begin op_TFR = 1; lr = postbyte0[7:4]; rr = postbyte0[3:0]; dr = postbyte0[3:0]; end
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8'hax, 8'hex: begin mode = `INDEXED; end
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endcase
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8'hbx, 8'hfx: begin mode = `EXTENDED; end
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end
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endcase
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4'h2:
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// Opcode type
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begin
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casex(opcode)
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mo = `REL8;
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8'h0e, 8'h6e, 8'h7e: op_JMP = 1;
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case (opcode[3:0])
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8'b10xx1101: op_JSR = 1; // bsr & jsr
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4'h0: begin end
|
endcase
|
4'h1: begin end
|
if (page2_valid == 1'b1)
|
4'h2: begin end
|
begin
|
4'h3: begin end
|
casex(postbyte0)
|
4'h4: begin end
|
8'h2x: mode = `REL16;
|
4'h5: begin end
|
8'h3f: op_SWI = 1;
|
4'h6: begin end
|
8'h83: begin mode = `IMMEDIATE; size = 1; end
|
4'h7: begin end
|
//8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end
|
4'h8: begin end
|
8'h8c: begin mode = `IMMEDIATE; size = 1; end
|
4'h9: begin end
|
//8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end
|
4'ha: begin end
|
8'h8e: begin mode = `IMMEDIATE; size = 1; end
|
4'hb: begin end
|
//8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end
|
4'hc: begin end
|
//8'h9f, 8'haf, 8'hbf: begin mem16 = 1; size = 1; end
|
4'hd: begin end
|
8'hce: begin mode = `IMMEDIATE; size = 1; end
|
4'he: begin end
|
//8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end
|
4'hf: begin end
|
//8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end
|
endcase
|
endcase
|
end
|
casex( postbyte0)
|
4'h3:
|
8'h9x, 8'hdx: mode = `DIRECT;
|
begin
|
8'hax, 8'hex: mode = `INDEXED;
|
case (opcode[3:0])
|
8'hbx, 8'hfx: mode = `EXTENDED;
|
4'h0: begin mo = `INDEXED; op_LEA = 1; dr = `RN_IX; end
|
endcase
|
4'h1: begin mo = `INDEXED; op_LEA = 1; dr = `RN_IY; end
|
end
|
4'h2: begin mo = `INDEXED; op_LEA = 1; dr = `RN_S; end
|
if (page3_valid == 1'b1)
|
4'h3: begin mo = `INDEXED; op_LEA = 1; dr = `RN_U; end
|
begin
|
4'h4: begin op_PUSH = 1; end
|
casex(postbyte0)
|
4'h5: begin op_PULL = 1; end
|
8'h3f: op_SWI = 1;
|
4'h6: begin op_PUSH = 1; ss = 0; end
|
8'h83: begin mode = `IMMEDIATE; size = 1; end // CMPD
|
4'h7: begin op_PULL = 1; ss = 0; end
|
//8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end // CMPD
|
4'h8: begin end
|
8'h8c: begin mode = `IMMEDIATE; size = 1; end
|
4'h9: begin mo = `INHERENT; op_RTS = 1; end
|
//8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end
|
4'ha: begin mo = `INHERENT; lr = `RN_ACCB; rr = `RN_IX; dr = `RN_IX; aop = `ADD; end // ABX
|
8'h8e: begin mode = `IMMEDIATE; size = 1; end
|
4'hb: begin mo = `INHERENT; op_RTI = 1; end
|
//8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end
|
4'hc: begin op_CWAI = 1; end
|
//8'h9f, 8'haf, 8'hbf: begin mem16 = 1; size = 1; end
|
4'hd: begin mo = `INHERENT; lr = `RN_ACCA; rr = `RN_ACCB; dr = `RN_ACCD; aop = `MUL; op_MUL = 1; end
|
8'hce: begin mode = `IMMEDIATE; size = 1; end
|
4'he: begin end
|
//8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end
|
4'hf: begin op_SWI = 1; end
|
//8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end
|
endcase
|
endcase
|
end
|
casex( postbyte0)
|
4'h4:
|
8'h9x, 8'hdx: mode = `DIRECT;
|
begin
|
8'hax, 8'hex: mode = `INDEXED;
|
mo = `INHERENT;
|
8'hbx, 8'hfx: mode = `EXTENDED;
|
case (opcode[3:0])
|
|
4'h0: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `NEG; end // NEG
|
|
4'h1: begin end
|
|
4'h2: begin end
|
|
4'h3: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `COM; end // COM
|
|
4'h4: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `LSR; end
|
|
4'h5: begin end
|
|
4'h6: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `ROR; end
|
|
4'h7: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `ASR; end
|
|
4'h8: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `LSL; end
|
|
4'h9: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `ROL; end
|
|
4'ha: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `DEC; end
|
|
4'hb: begin end
|
|
4'hc: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `INC; end
|
|
4'hd: begin lr = `RN_ACCA; aop = `TST; end
|
|
4'he: begin end
|
|
4'hf: begin dr = `RN_ACCA; aop = `CLR; end
|
endcase
|
endcase
|
end
|
end
|
|
4'h5:
|
|
begin
|
|
mo = `INHERENT;
|
|
case (opcode[3:0])
|
|
4'h0: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `NEG; end // NEG
|
|
4'h1: begin end
|
|
4'h2: begin end
|
|
4'h3: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `COM; end // COM
|
|
4'h4: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `LSR; end
|
|
4'h5: begin end
|
|
4'h6: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `ROR; end
|
|
4'h7: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `ASR; end
|
|
4'h8: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `LSL; end
|
|
4'h9: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `ROL; end
|
|
4'ha: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `DEC; end
|
|
4'hb: begin end
|
|
4'hc: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `INC; end
|
|
4'hd: begin lr = `RN_ACCB; aop = `TST; end
|
|
4'he: begin end
|
|
4'hf: begin dr = `RN_ACCB; aop = `CLR; end
|
|
endcase
|
|
end
|
|
4'h6:
|
|
begin
|
|
mo = `INDEXED;
|
|
case (opcode[3:0])
|
|
4'h0: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `NEG; end // NEG
|
|
4'h1: begin end
|
|
4'h2: begin end
|
|
4'h3: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `COM; end // COM
|
|
4'h4: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `LSR; end
|
|
4'h5: begin end
|
|
4'h6: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `ROR; end
|
|
4'h7: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `ASR; end
|
|
4'h8: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `LSL; end
|
|
4'h9: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `ROL; end
|
|
4'ha: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `DEC; end
|
|
4'hb: begin end
|
|
4'hc: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `INC; end
|
|
4'hd: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `AND; end// TST FIXME
|
|
4'he: begin op_JMP = 1; end // JMP
|
|
4'hf: begin dm = `MT_BYTE; aop = `CLR; end // CLR FIXME
|
|
endcase
|
|
end
|
|
4'h7:
|
|
begin
|
|
mo = `EXTENDED;
|
|
case (opcode[3:0])
|
|
4'h0: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `NEG; end // NEG
|
|
4'h1: begin end
|
|
4'h2: begin end
|
|
4'h3: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `COM; end // COM
|
|
4'h4: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `LSR; end
|
|
4'h5: begin end
|
|
4'h6: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `ROR; end
|
|
4'h7: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `ASR; end
|
|
4'h8: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `LSL; end
|
|
4'h9: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `ROL; end
|
|
4'ha: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `DEC; end
|
|
4'hb: begin end
|
|
4'hc: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `INC; end
|
|
4'hd: begin lm = `MT_BYTE; dm = `MT_BYTE; aop = `AND; end // TST FIXME
|
|
4'he: begin op_JMP = 1; end // JMP
|
|
4'hf: begin dm = `MT_BYTE; aop = `CLR; end // CLR FIXME
|
|
endcase
|
|
end
|
|
4'h8:
|
|
begin
|
|
mo = `IMMEDIATE; // right path filled in the right-path mux
|
|
case (opcode[3:0])
|
|
4'h0: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `SUB; end
|
|
4'h1: begin lr = `RN_ACCA; aop = `SUB; end // cmpa
|
|
4'h2: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `SBC; end
|
|
4'h3: begin lr = `RN_ACCD; dr = `RN_ACCD; aop = `SUB; end
|
|
4'h4: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `AND; end
|
|
4'h5: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `AND; end
|
|
4'h6: begin dr = `RN_ACCA; aop = `LD; end
|
|
4'h7: begin end
|
|
4'h8: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `EOR; end
|
|
4'h9: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `ADC; end
|
|
4'ha: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `OR; end
|
|
4'hb: begin lr = `RN_ACCA; dr = `RN_ACCA; aop = `ADD; end
|
|
4'hc: begin lr = `RN_IX; aop = `SUB; end // cmpx
|
|
4'hd: begin mo = `REL8; op_JSR = 1; end
|
|
4'he: begin dr = `RN_IX; aop = `LD; end
|
|
4'hf: begin end
|
|
endcase
|
|
end
|
|
4'h9:
|
|
begin
|
|
mo = `DIRECT;
|
|
case (opcode[3:0])
|
|
4'h0: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `SUB; end
|
|
4'h1: begin lr = `RN_ACCA; rm = `MT_BYTE; aop = `SUB; end // cmpa
|
|
4'h2: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `SBC; end
|
|
4'h3: begin lr = `RN_ACCD; rm = `MT_BYTE; dr = `RN_ACCD; aop = `SUB; end
|
|
4'h4: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `AND; end
|
|
4'h5: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `AND; end
|
|
4'h6: begin rm = `MT_BYTE; dr = `RN_ACCA; aop = `LD; end
|
|
4'h7: begin lr = `RN_ACCA; dm = `MT_BYTE; aop = `ST; end
|
|
4'h8: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `EOR; end
|
|
4'h9: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `ADC; end
|
|
4'ha: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `OR; end
|
|
4'hb: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `ADD; end
|
|
4'hc: begin lr = `RN_IX; rm = `MT_WORD; aop = `SUB; end // cmpx
|
|
4'hd: begin op_JSR = 1; end
|
|
4'he: begin rm = `MT_WORD; dr = `RN_IX; aop = `LD; end
|
|
4'hf: begin lr = `RN_IX; dm = `MT_WORD; aop = `ST; end
|
|
endcase
|
|
end
|
|
4'ha:
|
|
begin
|
|
mo = `INDEXED;
|
|
case (opcode[3:0])
|
|
4'h0: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `SUB; end
|
|
4'h1: begin lr = `RN_ACCA; rm = `MT_BYTE; aop = `SUB; end // cmpa
|
|
4'h2: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `SBC; end
|
|
4'h3: begin lr = `RN_ACCD; rm = `MT_BYTE; dr = `RN_ACCD; aop = `SUB; end
|
|
4'h4: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `AND; end
|
|
4'h5: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `AND; end
|
|
4'h6: begin rm = `MT_BYTE; dr = `RN_ACCA; aop = `LD; end
|
|
4'h7: begin lr = `RN_ACCA; dm = `MT_BYTE; aop = `ST; end
|
|
4'h8: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `EOR; end
|
|
4'h9: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `ADC; end
|
|
4'ha: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `OR; end
|
|
4'hb: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `ADD; end
|
|
4'hc: begin lr = `RN_IX; rm = `MT_WORD; aop = `SUB; end // cmpx
|
|
4'hd: begin op_JSR = 1; end
|
|
4'he: begin rm = `MT_WORD; dr = `RN_IX; aop = `LD; end
|
|
4'hf: begin lr = `RN_IX; dm = `MT_WORD; aop = `ST; end
|
|
endcase
|
|
end
|
|
4'hb:
|
|
begin
|
|
mo = `EXTENDED;
|
|
case (opcode[3:0])
|
|
4'h0: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `SUB; end
|
|
4'h1: begin lr = `RN_ACCA; rm = `MT_BYTE; aop = `SUB; end // cmpa
|
|
4'h2: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `SBC; end
|
|
4'h3: begin lr = `RN_ACCD; rm = `MT_BYTE; dr = `RN_ACCD; aop = `SUB; end
|
|
4'h4: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `AND; end
|
|
4'h5: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `AND; end
|
|
4'h6: begin rm = `MT_BYTE; dr = `RN_ACCA; aop = `LD; end
|
|
4'h7: begin lr = `RN_ACCA; dm = `MT_BYTE; aop = `ST; end
|
|
4'h8: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `EOR; end
|
|
4'h9: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `ADC; end
|
|
4'ha: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `OR; end
|
|
4'hb: begin lr = `RN_ACCA; rm = `MT_BYTE; dr = `RN_ACCA; aop = `ADD; end
|
|
4'hc: begin lr = `RN_IX; rm = `MT_WORD; aop = `SUB; end // cmpx
|
|
4'hd: begin op_JSR = 1; end
|
|
4'he: begin rm = `MT_WORD; dr = `RN_IX; aop = `LD; end
|
|
4'hf: begin lr = `RN_IX; dm = `MT_WORD; aop = `ST; end
|
|
endcase
|
|
end
|
|
4'hc:
|
|
begin
|
|
mo = `IMMEDIATE; // right path filled in the right-path mux
|
|
case (opcode[3:0])
|
|
4'h0: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `SUB; end
|
|
4'h1: begin lr = `RN_ACCB; aop = `SUB; end // cmp
|
|
4'h2: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `SBC; end
|
|
4'h3: begin sz = 1; lr = `RN_ACCD; dr = `RN_ACCD; aop = `ADD; end
|
|
4'h4: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `AND; end
|
|
4'h5: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `AND; end // bit
|
|
4'h6: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `LD; end
|
|
4'h7: begin end
|
|
4'h8: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `EOR; end
|
|
4'h9: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `ADC; end
|
|
4'ha: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `OR; end
|
|
4'hb: begin lr = `RN_ACCB; dr = `RN_ACCB; aop = `ADD; end
|
|
4'hc: begin sz = 1; dr = `RN_ACCD; aop = `LD; end
|
|
4'hd: begin end
|
|
4'he: begin sz = 1; dr = `RN_U; aop = `LD; end
|
|
4'hf: begin end
|
|
endcase
|
|
end
|
|
4'hd:
|
|
begin
|
|
mo = `DIRECT;
|
|
case (opcode[3:0])
|
|
4'h0: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `SUB; end
|
|
4'h1: begin lr = `RN_ACCB; rm = `MT_BYTE; aop = `SUB; end // cmp
|
|
4'h2: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `SBC; end
|
|
4'h3: begin lr = `RN_ACCD; rm = `MT_BYTE; dr = `RN_ACCD; aop = `ADD; end
|
|
4'h4: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `AND; end
|
|
4'h5: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `AND; end // bit
|
|
4'h6: begin rm = `MT_BYTE; dr = `RN_ACCB; aop = `LD; end
|
|
4'h7: begin lr = `RN_ACCB; dm = `MT_BYTE; aop = `ST; end
|
|
4'h8: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `EOR; end
|
|
4'h9: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `ADC; end
|
|
4'ha: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `OR; end
|
|
4'hb: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `ADD; end
|
|
4'hc: begin rm = `MT_WORD; dr = `RN_ACCD; aop = `LD; end
|
|
4'hd: begin lr = `RN_ACCD; dm = `MT_WORD; aop = `ST; end
|
|
4'he: begin rm = `MT_WORD; dr = `RN_U; aop = `LD; end
|
|
4'hf: begin lr = `RN_U; dm = `MT_WORD; aop = `ST; end
|
|
endcase
|
|
|
|
end
|
|
4'he:
|
|
begin
|
|
mo = `INDEXED;
|
|
case (opcode[3:0])
|
|
4'h0: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `SUB; end
|
|
4'h1: begin lr = `RN_ACCB; rm = `MT_BYTE; aop = `SUB; end // cmp
|
|
4'h2: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `SBC; end
|
|
4'h3: begin lr = `RN_ACCD; rm = `MT_BYTE; dr = `RN_ACCD; aop = `ADD; end
|
|
4'h4: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `AND; end
|
|
4'h5: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `AND; end // bit
|
|
4'h6: begin rm = `MT_BYTE; dr = `RN_ACCB; aop = `LD; end
|
|
4'h7: begin lr = `RN_ACCB; dm = `MT_BYTE; aop = `ST; end
|
|
4'h8: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `EOR; end
|
|
4'h9: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `ADC; end
|
|
4'ha: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `OR; end
|
|
4'hb: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `ADD; end
|
|
4'hc: begin rm = `MT_WORD; dr = `RN_ACCD; aop = `LD; end
|
|
4'hd: begin lr = `RN_ACCD; dm = `MT_WORD; aop = `ST; end
|
|
4'he: begin rm = `MT_WORD; dr = `RN_U; aop = `LD; end
|
|
4'hf: begin lr = `RN_U; dm = `MT_WORD; aop = `ST; end
|
|
endcase
|
|
|
|
end
|
|
4'hf:
|
|
begin
|
|
mo = `EXTENDED;
|
|
case (opcode[3:0])
|
|
4'h0: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `SUB; end
|
|
4'h1: begin lr = `RN_ACCB; rm = `MT_BYTE; aop = `SUB; end // cmp
|
|
4'h2: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `SBC; end
|
|
4'h3: begin lr = `RN_ACCD; rm = `MT_BYTE; dr = `RN_ACCD; aop = `ADD; end
|
|
4'h4: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `AND; end
|
|
4'h5: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `AND; end // bit
|
|
4'h6: begin rm = `MT_BYTE; dr = `RN_ACCB; aop = `LD; end
|
|
4'h7: begin lr = `RN_ACCB; dm = `MT_BYTE; aop = `ST; end
|
|
4'h8: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `EOR; end
|
|
4'h9: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `ADC; end
|
|
4'ha: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `OR; end
|
|
4'hb: begin lr = `RN_ACCB; rm = `MT_BYTE; dr = `RN_ACCB; aop = `ADD; end
|
|
4'hc: begin rm = `MT_WORD; dr = `RN_ACCD; aop = `LD; end
|
|
4'hd: begin lr = `RN_ACCD; dm = `MT_WORD; aop = `ST; end
|
|
4'he: begin rm = `MT_WORD; dr = `RN_U; aop = `LD; end
|
|
4'hf: begin lr = `RN_U; dm = `MT_WORD; aop = `ST; end
|
|
endcase
|
|
end
|
|
endcase
|
|
if (p2)
|
|
case (postbyte0[7:4])
|
|
4'h0, 4'h1, 4'h4, 4'h5, 4'h6, 4'h7: begin end
|
|
4'h2: mo = `REL16;
|
|
4'h3: if (postbyte0[3:0] == 4'hf) op_SWI = 1;
|
|
4'h8:
|
|
begin
|
|
case (postbyte0[3:0])
|
|
4'h0: begin end
|
|
4'h1: begin end
|
|
4'h2: begin end
|
|
4'h3: begin mo = `IMMEDIATE; sz = 1; lr = `RN_ACCD; aop = `SUB; end // cmpd
|
|
4'h4: begin end
|
|
4'h5: begin end
|
|
4'h6: begin end
|
|
4'h7: begin end
|
|
4'h8: begin end
|
|
4'h9: begin end
|
|
4'ha: begin end
|
|
4'hb: begin end
|
|
4'hc: begin mo = `IMMEDIATE; sz = 1; lr = `RN_IY; aop = `SUB; end
|
|
4'hd: begin end
|
|
4'he: begin mo = `IMMEDIATE; sz = 1; dr = `RN_IY; aop = `LD; end
|
|
4'hf: begin end
|
|
endcase
|
|
end
|
|
4'h9:
|
|
begin
|
|
case (postbyte0[3:0])
|
|
4'h0: begin end
|
|
4'h1: begin end
|
|
4'h2: begin end
|
|
4'h3: begin mo = `DIRECT; lr = `RN_ACCD; rm = `MT_WORD; aop = `SUB; end // cmpd
|
|
4'h4: begin end
|
|
4'h5: begin end
|
|
4'h6: begin end
|
|
4'h7: begin end
|
|
4'h8: begin end
|
|
4'h9: begin end
|
|
4'ha: begin end
|
|
4'hb: begin end
|
|
4'hc: begin mo = `DIRECT; lr = `RN_IY; rm = `MT_WORD; aop = `SUB; end
|
|
4'hd: begin end
|
|
4'he: begin mo = `DIRECT; rm = `MT_WORD; dr = `RN_IY; aop = `LD; end
|
|
4'hf: begin mo = `DIRECT; lr = `RN_IY; dm = `MT_WORD; aop = `ST; end
|
|
endcase
|
|
end
|
|
4'ha:
|
|
begin
|
|
case (postbyte0[3:0])
|
|
4'h0: begin end
|
|
4'h1: begin end
|
|
4'h2: begin end
|
|
4'h3: begin mo = `INDEXED; lr = `RN_ACCD; rm = `MT_WORD; aop = `SUB; end // cmpd
|
|
4'h4: begin end
|
|
4'h5: begin end
|
|
4'h6: begin end
|
|
4'h7: begin end
|
|
4'h8: begin end
|
|
4'h9: begin end
|
|
4'ha: begin end
|
|
4'hb: begin end
|
|
4'hc: begin mo = `INDEXED; lr = `RN_IY; rm = `MT_WORD; aop = `SUB; end
|
|
4'hd: begin end
|
|
4'he: begin mo = `INDEXED; rm = `MT_WORD; dr = `RN_IY; aop = `LD; end
|
|
4'hf: begin mo = `INDEXED; lr = `RN_IY; dm = `MT_WORD; aop = `ST; end
|
|
endcase
|
|
end
|
|
4'hb:
|
|
begin
|
|
case (postbyte0[3:0])
|
|
4'h0: begin end
|
|
4'h1: begin end
|
|
4'h2: begin end
|
|
4'h3: begin mo = `EXTENDED; lr = `RN_ACCD; rm = `MT_WORD; aop = `SUB; end // cmpd
|
|
4'h4: begin end
|
|
4'h5: begin end
|
|
4'h6: begin end
|
|
4'h7: begin end
|
|
4'h8: begin end
|
|
4'h9: begin end
|
|
4'ha: begin end
|
|
4'hb: begin end
|
|
4'hc: begin mo = `EXTENDED; lr = `RN_IY; rm = `MT_WORD; aop = `SUB; end
|
|
4'hd: begin end
|
|
4'he: begin mo = `EXTENDED; rm = `MT_WORD; dr = `RN_IY; aop = `LD; end
|
|
4'hf: begin mo = `EXTENDED; lr = `RN_IY; dm = `MT_WORD; aop = `ST; end
|
|
endcase
|
|
end
|
|
4'hc:
|
|
begin
|
|
case (postbyte0[3:0])
|
|
4'h0: begin end
|
|
4'h1: begin end
|
|
4'h2: begin end
|
|
4'h3: begin end
|
|
4'h4: begin end
|
|
4'h5: begin end
|
|
4'h6: begin end
|
|
4'h7: begin end
|
|
4'h8: begin end
|
|
4'h9: begin end
|
|
4'ha: begin end
|
|
4'hb: begin end
|
|
4'hc: begin end
|
|
4'hd: begin end
|
|
4'he: begin mo = `IMMEDIATE; sz = 1; dr = `RN_S; aop = `LD; end
|
|
4'hf: begin end
|
|
endcase
|
|
end
|
|
4'hd:
|
|
begin
|
|
case (postbyte0[3:0])
|
|
4'h0: begin end
|
|
4'h1: begin end
|
|
4'h2: begin end
|
|
4'h3: begin end
|
|
4'h4: begin end
|
|
4'h5: begin end
|
|
4'h6: begin end
|
|
4'h7: begin end
|
|
4'h8: begin end
|
|
4'h9: begin end
|
|
4'ha: begin end
|
|
4'hb: begin end
|
|
4'hc: begin end
|
|
4'hd: begin end
|
|
4'he: begin mo = `DIRECT; rm = `MT_WORD; dr = `RN_S; aop = `LD; end
|
|
4'hf: begin mo = `DIRECT; lr = `RN_S; dm = `MT_WORD; aop = `ST; end
|
|
endcase
|
|
end
|
|
4'he:
|
|
begin
|
|
case (postbyte0[3:0])
|
|
4'h0: begin end
|
|
4'h1: begin end
|
|
4'h2: begin end
|
|
4'h3: begin end
|
|
4'h4: begin end
|
|
4'h5: begin end
|
|
4'h6: begin end
|
|
4'h7: begin end
|
|
4'h8: begin end
|
|
4'h9: begin end
|
|
4'ha: begin end
|
|
4'hb: begin end
|
|
4'hc: begin end
|
|
4'hd: begin end
|
|
4'he: begin mo = `INDEXED; rm = `MT_WORD; dr = `RN_S; aop = `LD; end
|
|
4'hf: begin mo = `INDEXED; lr = `RN_S; dm = `MT_WORD; aop = `ST; end
|
|
endcase
|
|
end
|
|
4'hf:
|
|
begin
|
|
case (postbyte0[3:0])
|
|
4'h0: begin end
|
|
4'h1: begin end
|
|
4'h2: begin end
|
|
4'h3: begin end // cmpd
|
|
4'h4: begin end
|
|
4'h5: begin end
|
|
4'h6: begin end
|
|
4'h7: begin end
|
|
4'h8: begin end
|
|
4'h9: begin end
|
|
4'ha: begin end
|
|
4'hb: begin end
|
|
4'hc: begin end
|
|
4'hd: begin end
|
|
4'he: begin mo = `EXTENDED; rm = `MT_WORD; dr = `RN_S; aop = `LD; end
|
|
4'hf: begin mo = `EXTENDED; lr = `RN_S; dm = `MT_WORD; aop = `ST; end
|
|
endcase
|
|
end
|
|
endcase
|
|
if (p3)
|
|
case (postbyte0[7:4])
|
|
4'h0, 4'h1, 4'h4, 4'h5, 4'h6, 4'h7,
|
|
4'hc, 4'hd, 4'he, 4'hf: begin end
|
|
4'h3: if (postbyte0[3:0] == 4'hf) op_SWI = 1;
|
|
4'h8:
|
|
begin
|
|
case (postbyte0[3:0])
|
|
4'h0: begin end
|
|
4'h1: begin end
|
|
4'h2: begin end
|
|
4'h3: begin mo = `IMMEDIATE; sz = 1; lr = `RN_U; aop = `SUB; end // cmpd
|
|
4'h4: begin end
|
|
4'h5: begin end
|
|
4'h6: begin end
|
|
4'h7: begin end
|
|
4'h8: begin end
|
|
4'h9: begin end
|
|
4'ha: begin end
|
|
4'hb: begin end
|
|
4'hc: begin mo = `IMMEDIATE; sz = 1; lr = `RN_S; aop = `SUB; end
|
|
4'hd: begin end
|
|
4'he: begin end
|
|
4'hf: begin end
|
|
endcase
|
|
end
|
|
4'h9:
|
|
begin
|
|
case (postbyte0[3:0])
|
|
4'h0: begin end
|
|
4'h1: begin end
|
|
4'h2: begin end
|
|
4'h3: begin mo = `DIRECT; lr = `RN_U; rm = `MT_WORD; aop = `SUB; end // cmpd
|
|
4'h4: begin end
|
|
4'h5: begin end
|
|
4'h6: begin end
|
|
4'h7: begin end
|
|
4'h8: begin end
|
|
4'h9: begin end
|
|
4'ha: begin end
|
|
4'hb: begin end
|
|
4'hc: begin mo = `DIRECT; lr = `RN_S; rm = `MT_WORD; aop = `SUB; end
|
|
4'hd: begin end
|
|
4'he: begin end
|
|
4'hf: begin end
|
|
endcase
|
|
end
|
|
4'ha:
|
|
begin
|
|
case (postbyte0[3:0])
|
|
4'h0: begin end
|
|
4'h1: begin end
|
|
4'h2: begin end
|
|
4'h3: begin mo = `INDEXED; lr = `RN_U; rm = `MT_WORD; aop = `SUB; end // cmpd
|
|
4'h4: begin end
|
|
4'h5: begin end
|
|
4'h6: begin end
|
|
4'h7: begin end
|
|
4'h8: begin end
|
|
4'h9: begin end
|
|
4'ha: begin end
|
|
4'hb: begin end
|
|
4'hc: begin mo = `INDEXED; lr = `RN_S; rm = `MT_WORD; aop = `SUB; end
|
|
4'hd: begin end
|
|
4'he: begin end
|
|
4'hf: begin end
|
|
endcase
|
|
end
|
|
4'hb:
|
|
begin
|
|
case (postbyte0[3:0])
|
|
4'h0: begin end
|
|
4'h1: begin end
|
|
4'h2: begin end
|
|
4'h3: begin mo = `EXTENDED; lr = `RN_U; rm = `MT_WORD; aop = `SUB; end // cmpd
|
|
4'h4: begin end
|
|
4'h5: begin end
|
|
4'h6: begin end
|
|
4'h7: begin end
|
|
4'h8: begin end
|
|
4'h9: begin end
|
|
4'ha: begin end
|
|
4'hb: begin end
|
|
4'hc: begin mo = `EXTENDED; lr = `RN_S; rm = `MT_WORD; aop = `SUB; end
|
|
4'hd: begin end
|
|
4'he: begin end
|
|
4'hf: begin end
|
|
endcase
|
|
end
|
|
endcase
|
|
|
|
end
|
|
always @(posedge clk_in)
|
|
begin
|
|
path_right_addr_lo <= rr;
|
|
path_left_addr_lo <= lr;
|
|
dest_reg_lo <= dr;
|
|
path_right_memtype_lo <= rm;
|
|
path_left_memtype_lo <= lm;
|
|
dest_memtype_lo <= dm;
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
/* Decodes the Effective Address postbyte
|
|
to recover size of offset to load and post-incr/pre-decr info
|
|
*/
|
|
module decode_ea(
|
module decode_ea(
|
input wire [7:0] eapostbyte,
|
input wire [7:0] eapostbyte,
|
output reg noofs,
|
output reg [3:0] eabase_o, // base register
|
output reg ofs8, // needs an 8 bit offset
|
output reg [3:0] eaindex_o, // index register
|
output reg ofs16, // needs an 16 bit offset
|
output reg ea_ofs5_o,
|
output reg write_post, // needs to write back a predecr or post incr
|
output reg ea_ofs8_o,
|
output wire isind // signals when the mode is indirect, the memory at the address is read to load the real address
|
output reg ea_ofs16_o,
|
|
output wire ea_is_indirect_o,
|
|
output reg ea_write_back_o
|
);
|
);
|
|
|
assign isind = (eapostbyte[7] & eapostbyte[4]) ? 1'b1:1'b0;
|
assign ea_is_indirect_o = eapostbyte[7] & eapostbyte[4];
|
|
|
always @(*)
|
always @(*)
|
begin
|
begin
|
noofs = 0;
|
eabase_o = `RN_PC;
|
ofs8 = 0;
|
if (eapostbyte[7] & eapostbyte[3] & eapostbyte[2] & (!eapostbyte[1]))
|
ofs16 = 0;
|
eabase_o = `RN_PC;
|
write_post = 0;
|
else
|
casex (eapostbyte)
|
casex (eapostbyte)
|
8'b0xxxxxxx, 8'b1xx00100: noofs = 1;
|
8'bx00_x_xxxx: eabase_o = `RN_IX;
|
8'b1xxx1000, 8'b1xxx1100: ofs8 = 1;
|
8'bx01_x_xxxx: eabase_o = `RN_IY;
|
8'b1xxx1001, 8'b1xxx1101: ofs16 = 1;
|
8'bx10_x_xxxx: eabase_o = `RN_U;
|
8'b1xx11111: ofs16 = 1; // extended indirect
|
8'bx11_x_xxxx: eabase_o = `RN_S;
|
8'b1xxx00xx: write_post = 1;
|
|
endcase
|
endcase
|
end
|
end
|
endmodule
|
|
|
|
module decode_alu(
|
|
input wire [7:0] opcode,
|
|
input wire [7:0] postbyte0,
|
|
input wire page2_valid, // is 1 when the postbyte0 was loaded and is page2 opcode
|
|
input wire page3_valid, // is 1 when the postbyte0 was loaded and is page3 opcode
|
|
output reg [4:0] alu_opcode,
|
|
output reg [1:0] dec_alu_right_path_mod,
|
|
output wire dest_flags
|
|
);
|
|
// flags are written for alu opcodes as long as the opcode is not ANDCC or ORCC
|
|
assign dest_flags = (alu_opcode != `NOP) && (opcode != 8'h1a) && (opcode != 8'h1c);
|
|
always @(*)
|
always @(*)
|
begin
|
begin
|
alu_opcode = `NOP;
|
ea_ofs5_o = 1'b0;
|
dec_alu_right_path_mod = `MOD_DEFAULT;
|
ea_ofs8_o = 1'b0;
|
casex (opcode)
|
ea_ofs16_o = 1'b0;
|
8'b1xxx_0000: alu_opcode = `SUB;
|
ea_write_back_o = 1'b0;
|
8'b1xxx_0001: alu_opcode = `SUB; // CMP
|
casex (eapostbyte)
|
8'b1xxx_0010: alu_opcode = `SBC;
|
8'b0xx0xxxx: // base + 5 bit signed offset +
|
8'b10xx_0011: alu_opcode = `SUB;
|
ea_ofs5_o = 1'b1;
|
8'b11xx_0011: alu_opcode = `ADD;
|
8'b0xx1xxxx: // 5 bit signed offset -
|
8'b1xxx_0100: alu_opcode = `AND;
|
ea_ofs5_o = 1'b1;
|
8'b1xxx_0101: alu_opcode = `AND; // BIT
|
8'b1xx_x_0000, // post increment, increment occurs at a later stage
|
8'b1xxx_0110: alu_opcode = `LD;
|
8'b1xx_x_0001: ea_write_back_o = 1'b1;
|
8'b1xxx_0111: alu_opcode = `ST;
|
8'b1xx_x_0100: begin end
|
8'b1xxx_1000: alu_opcode = `EOR;
|
8'b1xx_x_0010, // pre decrement
|
8'b1xxx_1001: alu_opcode = `ADC;
|
8'b1xx_x_0011: ea_write_back_o = 1'b1;
|
8'b1xxx_1010: alu_opcode = `OR;
|
8'b1xx_x_0101: // B,R
|
8'b1xxx_1011: alu_opcode = `ADD;
|
eaindex_o = `RN_ACCB;
|
8'b10xx_1100: alu_opcode = `SUB; // CMP
|
8'b1xx_x_0110: // A,R
|
8'b11xx_1100: alu_opcode = `LD;
|
eaindex_o = `RN_ACCA;
|
8'b11xx_1101: alu_opcode = `ST;
|
8'b1xx_x_1011: // D,R
|
8'b1xxx_1110: alu_opcode = `LD;
|
eaindex_o = `RN_ACCD;
|
8'b1xxx_1111: alu_opcode = `ST;
|
8'b1xx_x_1000: // n,R 8 bit offset
|
|
ea_ofs8_o = 1'b1;
|
8'h00, 8'b01xx_0000: alu_opcode = `NEG;
|
8'b1xx_x_1001: // n,R // 16 bit offset
|
8'h03, 8'b01xx_0011: alu_opcode = `COM;
|
ea_ofs16_o = 1'b1;
|
8'h04, 8'b01xx_0100: alu_opcode = `LSR;
|
8'b1xx_x_1100: // n,PC
|
8'h06, 8'b01xx_0110: alu_opcode = `ROR;
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ea_ofs8_o = 1'b1;
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8'h07, 8'b01xx_0111: alu_opcode = `ASR;
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8'b1xx_x_1101: // n,PC
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8'h08, 8'b01xx_1000: alu_opcode = `LSL;
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ea_ofs16_o = 1'b1;
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8'h09, 8'b01xx_1001: alu_opcode = `ROL;
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8'h0a, 8'b01xx_1010: begin alu_opcode = `DEC; dec_alu_right_path_mod = `MOD_ONE; end // dec
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8'h0c, 8'b01xx_1100: begin alu_opcode = `INC; dec_alu_right_path_mod = `MOD_ONE; end // inc
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8'h0d, 8'b01xx_1101: alu_opcode = `AND;
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8'h0f, 8'b01xx_1111: begin alu_opcode = `LD; dec_alu_right_path_mod = `MOD_ZERO; end // CLR
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8'h19: alu_opcode = `DAA;
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8'h1a: alu_opcode = `OR;
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8'h1c: alu_opcode = `AND;
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8'h1d: alu_opcode = `SEXT;
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//8'h1e: alu_opcode = `EXG;
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8'b0011_000x: alu_opcode = `LEA;
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8'h3d: alu_opcode = `MUL;
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endcase
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if (page2_valid)
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casex (postbyte0)
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8'b10xx_0011,
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8'b10xx_1100: alu_opcode = `SUB; //CMP
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8'b1xxx_1110: alu_opcode = `LD;
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8'b1xxx_1111: alu_opcode = `ST;
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endcase
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if (page3_valid)
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casex (postbyte0)
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8'b10xx_0011,
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8'b10xx_1100: alu_opcode = `SUB; //CMP
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8'b1xxx_1110: alu_opcode = `LD;
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8'b1xxx_1111: alu_opcode = `ST;
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endcase
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endcase
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end
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end
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|
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endmodule
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endmodule
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/* decodes the condition and checks the flags to see if it is met */
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/* decodes the condition and checks the flags to see if it is met */
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module test_condition(
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module test_condition(
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input wire [7:0] opcode,
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input wire [7:0] opcode,
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input wire [7:0] postbyte0,
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input wire [7:0] postbyte0,
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input wire page2_valid,
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input wire page2_valid,
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