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*
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*
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*
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*
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*/
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*/
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`include "defs.v"
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`include "defs.v"
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module decode_regs(
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module decode_regs(
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input wire cpu_clk,
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input wire [7:0] opcode,
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input wire [7:0] opcode,
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input wire [7:0] postbyte0,
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input wire [7:0] postbyte0,
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input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
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output reg [3:0] path_left_addr,
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output reg [3:0] path_left_addr_o,
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output reg [3:0] path_right_addr,
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output reg [3:0] path_right_addr_o,
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output reg [3:0] dest_reg,
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output reg [3:0] dest_reg_o,
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output wire write_dest,
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output wire write_dest,
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output wire source_size,
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output wire source_size,
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output wire result_size
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output wire result_size
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);
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);
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reg [3:0] path_left_addr, path_right_addr, dest_reg;
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// for registers, memory writes are handled differently
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// for registers, memory writes are handled differently
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assign write_dest = (dest_reg != `RN_INV);
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assign write_dest = (dest_reg != `RN_INV);
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assign source_size = (path_left_addr < `RN_ACCA);
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assign source_size = (path_left_addr < `RN_ACCA);
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assign result_size = (dest_reg < `RN_IMM16) ? 1:0;
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assign result_size = (dest_reg < `RN_IMM16) ? 1:0;
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always @(opcode, postbyte0, page2_valid, page3_valid)
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always @(opcode, postbyte0, page2_valid, page3_valid)
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| Line 86... |
Line 88... |
4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
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4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
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default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
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default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
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endcase
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endcase
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8'h4x, 8'h8x, 8'h9x, 8'hax, 8'hbx:
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8'h4x, 8'h8x, 8'h9x, 8'hax, 8'hbx:
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case (opcode[3:0])
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case (opcode[3:0])
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4'h1: path_left_addr = `RN_ACCA; // CMP
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4'h1, 4'h5: path_left_addr = `RN_ACCA; // CMP, BIT
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4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
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4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
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4'h7: begin path_left_addr = `RN_ACCA; dest_reg = `RN_MEM8; end
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4'h7: begin path_left_addr = `RN_ACCA; dest_reg = `RN_MEM8; end
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4'hc: path_left_addr = `RN_IX; // cmpx
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4'hc: path_left_addr = `RN_IX; // cmpx
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4'he, 4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end
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4'he, 4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end
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4'hd: begin end // nothing active, jsr
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4'hd: begin end // nothing active, jsr
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default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
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default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
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endcase
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endcase
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8'h5x, 8'hcx, 8'hdx, 8'hex, 8'hfx:
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8'h5x, 8'hcx, 8'hdx, 8'hex, 8'hfx:
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case (opcode[3:0])
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case (opcode[3:0])
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4'h1: path_left_addr = `RN_ACCB; // CMP
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4'h1, 4'h5: path_left_addr = `RN_ACCB; // CMP, BIT
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4'h3, 4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
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4'h3, 4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
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4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // store to mem
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4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // store to mem
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4'he: begin path_left_addr = `RN_U; dest_reg = `RN_IX; end
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4'he: begin path_left_addr = `RN_U; dest_reg = `RN_IX; end
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4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end
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4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end
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4'hd: begin path_left_addr = `RN_ACCD; end
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4'hd: begin path_left_addr = `RN_ACCD; end
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Line 124... |
8'b1x1x_0011, 8'b1x1x_11x0, 8'b1x1x_1111: path_right_addr = `RN_MEM16;
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8'b1x1x_0011, 8'b1x1x_11x0, 8'b1x1x_1111: path_right_addr = `RN_MEM16;
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8'b1x1x_010x, 8'b1x1x_0110,
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8'b1x1x_010x, 8'b1x1x_0110,
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8'b1x1x_10xx: path_right_addr = `RN_MEM8;
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8'b1x1x_10xx: path_right_addr = `RN_MEM8;
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endcase
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endcase
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end
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end
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always @(posedge cpu_clk)
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begin
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path_right_addr_o <= path_right_addr;
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path_left_addr_o <= path_left_addr;
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dest_reg_o <= dest_reg;
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end
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endmodule
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endmodule
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/* Decodes module and addressing mode for page 1 opcodes */
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/* Decodes module and addressing mode for page 1 opcodes */
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module decode_op(
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module decode_op(
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input wire [7:0] opcode,
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input wire [7:0] opcode,
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Line 304... |
begin
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begin
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alu_opcode = `NOP;
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alu_opcode = `NOP;
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dec_alu_right_path_mod = `MOD_DEFAULT;
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dec_alu_right_path_mod = `MOD_DEFAULT;
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casex (opcode)
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casex (opcode)
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8'b1xxx_0000: alu_opcode = `SUB;
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8'b1xxx_0000: alu_opcode = `SUB;
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8'b1xxx_0001: alu_opcode = `CMP;
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8'b1xxx_0001: alu_opcode = `SUB; // CMP
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8'b1xxx_0010: alu_opcode = `SBC;
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8'b1xxx_0010: alu_opcode = `SBC;
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8'b10xx_0011: alu_opcode = `SUB;
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8'b10xx_0011: alu_opcode = `SUB;
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8'b11xx_0011: alu_opcode = `ADD;
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8'b11xx_0011: alu_opcode = `ADD;
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8'b1xxx_0100: alu_opcode = `AND;
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8'b1xxx_0100: alu_opcode = `AND;
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8'b1xxx_0101: alu_opcode = `BIT;
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8'b1xxx_0101: alu_opcode = `AND; // BIT
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8'b1xxx_0110: alu_opcode = `LD;
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8'b1xxx_0110: alu_opcode = `LD;
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8'b1xxx_0111: alu_opcode = `ST;
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8'b1xxx_0111: alu_opcode = `ST;
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8'b1xxx_1000: alu_opcode = `EOR;
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8'b1xxx_1000: alu_opcode = `EOR;
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8'b1xxx_1001: alu_opcode = `ADC;
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8'b1xxx_1001: alu_opcode = `ADC;
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8'b1xxx_1010: alu_opcode = `OR;
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8'b1xxx_1010: alu_opcode = `OR;
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8'b1xxx_1011: alu_opcode = `ADD;
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8'b1xxx_1011: alu_opcode = `ADD;
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8'b10xx_1100: alu_opcode = `CMP;
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8'b10xx_1100: alu_opcode = `SUB; // CMP
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8'b11xx_1100: alu_opcode = `LD;
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8'b11xx_1100: alu_opcode = `LD;
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8'b11xx_1101: alu_opcode = `LD;
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8'b11xx_1101: alu_opcode = `LD;
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8'b1xxx_1110: alu_opcode = `LD;
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8'b1xxx_1110: alu_opcode = `LD;
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8'b1xxx_1111: alu_opcode = `ST;
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8'b1xxx_1111: alu_opcode = `ST;
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Line 338... |
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8'h19: alu_opcode = `DAA;
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8'h19: alu_opcode = `DAA;
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8'h1a: alu_opcode = `ORCC;
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8'h1a: alu_opcode = `ORCC;
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8'h1c, 8'h3c: alu_opcode = `ANDCC;
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8'h1c, 8'h3c: alu_opcode = `ANDCC;
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8'h1d: alu_opcode = `SEXT;
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8'h1d: alu_opcode = `SEXT;
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8'h1e: alu_opcode = `EXG;
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//8'h1e: alu_opcode = `EXG;
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8'b0011_000x: alu_opcode = `LEA;
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8'b0011_000x: alu_opcode = `LEA;
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8'h3d: alu_opcode = `MUL;
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8'h3d: alu_opcode = `MUL;
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endcase
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endcase
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if (page2_valid)
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if (page2_valid)
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casex (postbyte0)
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casex (postbyte0)
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8'b10xx_0011,
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8'b10xx_0011,
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8'b10xx_1010: alu_opcode = `CMP;
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8'b10xx_1010: alu_opcode = `SUB; //CMP
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8'b1xxx_1110: alu_opcode = `LD;
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8'b1xxx_1110: alu_opcode = `LD;
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8'b1xxx_1111: alu_opcode = `ST;
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8'b1xxx_1111: alu_opcode = `ST;
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endcase
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endcase
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if (page3_valid)
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if (page3_valid)
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casex (postbyte0)
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casex (postbyte0)
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8'b10xx_0011,
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8'b10xx_0011,
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8'b10xx_1010: alu_opcode = `CMP;
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8'b10xx_1010: alu_opcode = `SUB; //CMP
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8'b1xxx_1110: alu_opcode = `LD;
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8'b1xxx_1110: alu_opcode = `LD;
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8'b1xxx_1111: alu_opcode = `ST;
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8'b1xxx_1111: alu_opcode = `ST;
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endcase
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endcase
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end
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end
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