URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [defs.v] - Diff between revs 9 and 12

Rev 9	Rev 12
Line 32...	Line 32...
`define SUB 5'b01001 // in arith8	`define SUB 5'b01001 // in arith8
`define ADC 5'b01010 // in arith8	`define ADC 5'b01010 // in arith8
`define SBC 5'b01011 // in arith8	`define SBC 5'b01011 // in arith8

`define LSR 5'b10000	`define LSR 5'b10000
`define ROR 5'b10001	`define LSL 5'b10001
`define LSL 5'b10011	`define ROR 5'b10010
`define ROL 5'b10011	`define ROL 5'b10011
`define ASR 5'b10100	`define ASR 5'b10100
`define NEG 5'b10101	`define NEG 5'b10101
`define COM 5'b10110	`define COM 5'b10110
`define ORCC 5'b11000	`define INC 5'b11000 // encoding of least 2 bits must be like ADD/SUB
`define ANDCC 5'b11001	`define DEC 5'b11001
`define DAA 5'b11010	`define DAA 5'b11010
`define MUL 5'b11011	`define MUL 5'b11011
`define LEA 5'b11100	`define LEA 5'b11100

`/* Sequencer states */`	`/* Sequencer states */`
Line 147...	Line 147...
`define OP_NONE 3'h0	`define OP_NONE 3'h0
`define OP_PUSH 3'h1	`define OP_PUSH 3'h1
`define OP_PULL 3'h2	`define OP_PULL 3'h2
`define OP_RTS 3'h3	`define OP_RTS 3'h3
`define OP_JSR 3'h4	`define OP_JSR 3'h4
`define OP_ST 3'h5	`define OP_JMP 3'h5
`define OP_LD 3'h6	`define OP_LD 3'h6
`define OP_LEA 3'h7	`define OP_LEA 3'h7

`/* alu decoder right path modifier */`	`/* alu decoder right path modifier */`
`define MOD_DEFAULT 2'h0	`define MOD_DEFAULT 2'h0