URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [regblock.v] - Diff between revs 10 and 16

Rev 10	Rev 16
Line 74...	Line 74...
`// left path output, always 16 bits`	`// left path output, always 16 bits`
`always @(*)`	`always @(*)`
`begin`	`begin`
`case (path_left_addr)`	`case (path_left_addr)`
`RN_ACCA: path_left_data = { 8'hff, ACCA };	`RN_ACCA: path_left_data = { 8'hff, ACCA };
`RN_ACCB: path_left_data = { 8'hff, ACCB };	`RN_ACCB: path_left_data = { 8'h00, ACCB };
`RN_ACCD: path_left_data = `ACCD;	`RN_ACCD: path_left_data = `ACCD;
`RN_IX: path_left_data = IX;	`RN_IX: path_left_data = IX;
`RN_IY: path_left_data = IY;	`RN_IY: path_left_data = IY;
`RN_U: path_left_data = SU;	`RN_U: path_left_data = SU;
`RN_S: path_left_data = SS;	`RN_S: path_left_data = SS;
Line 93...	Line 93...
`// right path output, always 16 bits`	`// right path output, always 16 bits`
`always @(*)`	`always @(*)`
`begin`	`begin`
`case (path_right_addr)`	`case (path_right_addr)`
`RN_ACCA: path_right_data = { 8'hff, ACCA };	`RN_ACCA: path_right_data = { 8'hff, ACCA };
`RN_ACCB: path_right_data = { 8'hff, ACCB };	`RN_ACCB: path_right_data = { 8'h00, ACCB }; // FIXME
`RN_ACCD: path_right_data = `ACCD;	`RN_ACCD: path_right_data = `ACCD;
`RN_IX: path_right_data = IX;	`RN_IX: path_right_data = IX;
`RN_IY: path_right_data = IY;	`RN_IY: path_right_data = IY;
`RN_U: path_right_data = SU;	`RN_U: path_right_data = SU;
`RN_S: path_right_data = SS;	`RN_S: path_right_data = SS;