| Line 4... |
Line 4... |
#Hostname: node01.pacito.sys
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#Hostname: node01.pacito.sys
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#Implementation: P6809
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#Implementation: P6809
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$ Start of Compile
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$ Start of Compile
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#Mon Jan 6 06:54:11 2014
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#Thu Feb 6 15:34:32 2014
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Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013
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Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013
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@N|Running in 64-bit mode
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@N|Running in 64-bit mode
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Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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| Line 22... |
Line 22... |
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"
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@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"
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@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"
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@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":699:23:699:27|Specified digits overflow the number's size
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@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":732:23:732:27|Specified digits overflow the number's size
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v"
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Verilog syntax check successful!
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Verilog syntax check successful!
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File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v changed - recompiling
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File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v changed - recompiling
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Selecting top level module CC3_top
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Selecting top level module CC3_top
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":62:7:62:12|Synthesizing module logic8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":62:7:62:12|Synthesizing module logic8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:7:85:12|Synthesizing module arith8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:7:85:12|Synthesizing module arith8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":157:7:157:12|Synthesizing module shift8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":158:7:158:12|Synthesizing module shift8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":197:7:197:10|Synthesizing module alu8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":198:7:198:10|Synthesizing module alu8
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":319:0:319:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":320:0:320:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":240:12:240:13|No assignment to n8
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":241:12:241:13|No assignment to n8
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":240:20:240:21|No assignment to z8
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":241:20:241:21|No assignment to z8
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@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":301:0:301:5|Pruning register regq8[7:0]
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@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":302:0:302:5|Pruning register regq8[7:0]
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":603:7:603:12|Synthesizing module mul8x8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":604:7:604:12|Synthesizing module mul8x8
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":128:7:128:13|Synthesizing module arith16
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":129:7:129:13|Synthesizing module arith16
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":325:7:325:11|Synthesizing module alu16
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":326:7:326:11|Synthesizing module alu16
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":411:23:411:29|No assignment to wire arith_h
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":412:23:412:29|No assignment to wire arith_h
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@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":517:0:517:5|Pruning register regq16[15:0]
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@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":518:0:518:5|Pruning register regq16[15:0]
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":15:7:15:9|Synthesizing module alu
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":15:7:15:9|Synthesizing module alu
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":191:7:191:13|Synthesizing module calc_ea
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":191:7:191:13|Synthesizing module calc_ea
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| Line 73... |
Line 73... |
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":365:7:365:20|Synthesizing module test_condition
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":365:7:365:20|Synthesizing module test_condition
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu
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@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":418:6:418:13|Ignoring system task $display
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@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":450:6:450:13|Ignoring system task $display
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1039:0:1039:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1074:0:1074:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":64:11:64:23|No assignment to wire alu8_o_result
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":67:11:67:23|No assignment to wire alu8_o_result
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":65:11:65:20|No assignment to wire alu8_o_CCR
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":68:11:68:20|No assignment to wire alu8_o_CCR
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit k_mem_dest[0] is always 1, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit k_mem_dest[1] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit k_mem_dest[1] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit next_mem_state[1] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit next_mem_state[1] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit next_mem_state[2] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit next_mem_state[2] is always 0, optimizing ...
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@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bits 2 to 1 of next_mem_state[5:0]
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@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Pruning register bits 2 to 1 of next_mem_state[5:0]
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@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bit 1 of k_mem_dest[1:0]
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@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI
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@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI
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@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC
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@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC
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| Line 151... |
Line 152... |
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@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element redr.
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@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element redr.
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@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element greenr.
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@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element greenr.
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":10:7:10:13|Synthesizing module CC3_top
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":10:7:10:13|Synthesizing module CC3_top
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":31:14:31:21|No assignment to clk_div2
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:14:37:21|No assignment to clk_div2
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|No assignment to wire cpu1_addr_o
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":42:25:42:35|No assignment to wire cpu1_addr_o
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:40:37:51|No assignment to wire cpu1_data_in
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:40:43:51|No assignment to wire cpu1_data_in
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|No assignment to wire cpu1_data_out
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:54:43:66|No assignment to wire cpu1_data_out
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:23:38:29|No assignment to wire cpu1_we
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":44:23:44:29|No assignment to wire cpu1_we
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|
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:32:38:38|No assignment to wire cpu1_oe
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":44:32:44:38|No assignment to wire cpu1_oe
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@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
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@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:54:43:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
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@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
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@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":42:25:42:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
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@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":105:25:105:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.
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@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":146:25:146:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...
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| Line 179... |
Line 180... |
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...
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@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Pruning register bits 5 to 3 of next_push_state[5:0]
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@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bits 5 to 3 of next_push_state[5:0]
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@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":22:12:22:20|Input debug_clk is unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":369:18:369:20|Input port bits 7 to 4 of CCR[7:0] are unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":369:18:369:20|Input port bits 7 to 4 of CCR[7:0] are unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":294:18:294:26|Input port bits 5 to 4 of postbyte0[7:0] are unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":294:18:294:26|Input port bits 5 to 4 of postbyte0[7:0] are unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":267:18:267:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":267:18:267:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":329:18:329:20|Input port bits 7 to 4 of CCR[7:0] are unused
|
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":330:18:330:20|Input port bits 7 to 4 of CCR[7:0] are unused
|
|
|
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Pruning register bits 15 to 13 of pipe0[15:0]
|
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Pruning register bits 15 to 13 of pipe0[15:0]
|
|
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Register bit pipe0[12] is always 0, optimizing ...
|
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Register bit pipe0[12] is always 0, optimizing ...
|
@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Pruning register bit 12 of pipe0[12:0]
|
@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Pruning register bit 12 of pipe0[12:0]
|
|
|
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":198:12:198:17|Input clk_in is unused
|
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":199:12:199:17|Input clk_in is unused
|
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":159:18:159:21|Input b_in is unused
|
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":160:18:160:21|Input b_in is unused
|
@END
|
@END
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:04s realtime, 0h:00m:02s cputime
|
# Mon Jan 6 06:54:13 2014
|
# Thu Feb 6 15:34:36 2014
|
|
|
###########################################################]
|
###########################################################]
|
Premap Report
|
Premap Report
|
|
|
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
|
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
|
| Line 234... |
Line 236... |
|
|
Start Requested Requested Clock Clock
|
Start Requested Requested Clock Clock
|
Clock Frequency Period Type Group
|
Clock Frequency Period Type Group
|
--------------------------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------------------------
|
CC3_top|clk40_i 1.0 MHz 1000.000 inferred Inferred_clkgroup_0
|
CC3_top|clk40_i 1.0 MHz 1000.000 inferred Inferred_clkgroup_0
|
|
CC3_top|div_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0
|
CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0
|
CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0
|
====================================================================================================================
|
====================================================================================================================
|
|
|
@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 83 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 95 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
|
|
syn_allowed_resources : blockrams=26 set on top level netlist CC3_top
|
syn_allowed_resources : blockrams=26 set on top level netlist CC3_top
|
Finished Pre Mapping Phase.Pre-mapping successful!
|
Finished Pre Mapping Phase.Pre-mapping successful!
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 137MB)
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 137MB)
|
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
# Mon Jan 6 06:54:14 2014
|
# Thu Feb 6 15:34:40 2014
|
|
|
###########################################################]
|
###########################################################]
|
Map & Optimize Report
|
Map & Optimize Report
|
|
|
Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
|
Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
|
| Line 279... |
Line 282... |
|
|
Available hyper_sources - for debug and ip models
|
Available hyper_sources - for debug and ip models
|
None Found
|
None Found
|
|
|
|
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
|
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SS[15:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SS[15:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
|
|
Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 161MB)
|
Finished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 157MB peak: 159MB)
|
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
|
|
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 152MB peak: 163MB)
|
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 152MB peak: 160MB)
|
|
|
|
|
|
|
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 165MB)
|
|
|
|
@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":883:11:883:29|Pipelining module un75
|
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 160MB)
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register k_pp_regs[7:0] pushed in.
|
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":143:35:143:85|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_2[16:0] from cpu0.alu.alu16.a16.un28_q_out[16:0]
|
@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":222:2:222:5|Pipelining module ea_reg_post_o[15:0]
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":100:35:100:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.a8.q_out_2[8:0] from cpu0.alu.alu8.a8.un26_q_out[8:0]
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register IY[15:0] pushed in.
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":140:35:140:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_1_0[16:0] from cpu0.alu.alu16.a16.un17_q_out[16:0]
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register IX[15:0] pushed in.
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":99:35:99:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.a8.q_out_1_0[8:0] from cpu0.alu.alu8.a8.un17_q_out[8:0]
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_ind_ea[7:0] pushed in.
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":254:2:254:5|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.ea.k_new_pc_4[15:0] from cpu0.un1_regs_o_pc[15:0]
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register DP[7:0] pushed in.
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register ACCB[7:0] pushed in.
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register eflag pushed in.
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register fflag pushed in.
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register hflag pushed in.
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register intff pushed in.
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register nff pushed in.
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register zff pushed in.
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register vff pushed in.
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register cff pushed in.
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register PC[15:0] pushed in.
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register ACCA[7:0] pushed in.
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_write_pc pushed in.
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_inc_pc pushed in.
|
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":141:35:141:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_1_0[16:0] from cpu0.alu.alu16.a16.un17_q_out[16:0]
|
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":142:35:142:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_2[16:0] from cpu0.alu.alu16.a16.un28_q_out[16:0]
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]
|
|
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 152MB peak: 165MB)
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 160MB)
|
|
|
|
|
Finished Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 152MB peak: 165MB)
|
Finished Early Timing Optimization (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 160MB)
|
|
|
|
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 151MB peak: 165MB)
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:09s; Memory used current: 151MB peak: 160MB)
|
|
|
|
|
Finished preparing to map (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 151MB peak: 165MB)
|
Finished preparing to map (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:11s; Memory used current: 151MB peak: 160MB)
|
|
|
|
|
Finished technology mapping (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 212MB peak: 229MB)
|
Finished technology mapping (Real Time elapsed 0h:00m:24s; CPU Time elapsed 0h:00m:13s; Memory used current: 202MB peak: 230MB)
|
|
|
Pass CPU time Worst Slack Luts / Registers
|
Pass CPU time Worst Slack Luts / Registers
|
------------------------------------------------------------
|
------------------------------------------------------------
|
Pass CPU time Worst Slack Luts / Registers
|
Pass CPU time Worst Slack Luts / Registers
|
------------------------------------------------------------
|
------------------------------------------------------------
|
------------------------------------------------------------
|
------------------------------------------------------------
|
|
|
|
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 167MB peak: 229MB)
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:14s; Memory used current: 166MB peak: 230MB)
|
|
|
@N: FX164 |The option to pack flops in the IOB has not been specified
|
@N: FX164 |The option to pack flops in the IOB has not been specified
|
|
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 169MB peak: 229MB)
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:15s; Memory used current: 168MB peak: 230MB)
|
|
|
|
|
|
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
|
|
1 non-gated/non-generated clock tree(s) driving 455 clock pin(s) of sequential element(s)
|
1 non-gated/non-generated clock tree(s) driving 596 clock pin(s) of sequential element(s)
|
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
342 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks
|
264 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks
|
|
|
=========================== Non-Gated/Non-Generated Clocks ============================
|
=========================== Non-Gated/Non-Generated Clocks ============================
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
---------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------
|
@K:CKID0001 clk40_i port 455 cpu_clk
|
@K:CKID0001 clk40_i port 596 div
|
=======================================================================================
|
=======================================================================================
|
===== Gated/Generated Clocks =====
|
===== Gated/Generated Clocks =====
|
************** None **************
|
************** None **************
|
----------------------------------
|
----------------------------------
|
==================================
|
==================================
|
| Line 367... |
Line 383... |
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
|
|
Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srm
|
Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srm
|
|
|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 172MB peak: 229MB)
|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:28s; CPU Time elapsed 0h:00m:16s; Memory used current: 170MB peak: 230MB)
|
|
|
Writing EDIF Netlist and constraint files
|
Writing EDIF Netlist and constraint files
|
G-2012.09L-SP1
|
G-2012.09L-SP1
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
|
|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 176MB peak: 229MB)
|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:17s; Memory used current: 174MB peak: 230MB)
|
|
|
@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"
|
@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"
|
|
|
|
|
|
|
##### START OF TIMING REPORT #####[
|
##### START OF TIMING REPORT #####[
|
# Timing Report written on Mon Jan 6 06:54:29 2014
|
# Timing Report written on Thu Feb 6 15:35:10 2014
|
#
|
#
|
|
|
|
|
Top view: CC3_top
|
Top view: CC3_top
|
Requested Frequency: 1.0 MHz
|
Requested Frequency: 1.0 MHz
|
| Line 399... |
Line 415... |
|
|
Performance Summary
|
Performance Summary
|
*******************
|
*******************
|
|
|
|
|
Worst slack in design: 978.474
|
Worst slack in design: 978.937
|
|
|
Requested Estimated Requested Estimated Clock Clock
|
Requested Estimated Requested Estimated Clock Clock
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
------------------------------------------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------------------------------------------------
|
CC3_top|clk40_i 1.0 MHz 46.5 MHz 1000.000 21.526 978.474 inferred Inferred_clkgroup_0
|
CC3_top|clk40_i 1.0 MHz 47.5 MHz 1000.000 21.063 978.937 inferred Inferred_clkgroup_0
|
========================================================================================================================
|
========================================================================================================================
|
|
|
|
|
|
|
|
|
| Line 418... |
Line 434... |
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
--------------------------------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------------------------------
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
--------------------------------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------------------------------
|
CC3_top|clk40_i CC3_top|clk40_i | 1000.000 978.474 | No paths - | No paths - | No paths -
|
CC3_top|clk40_i CC3_top|clk40_i | 1000.000 978.937 | No paths - | No paths - | No paths -
|
==========================================================================================================================
|
==========================================================================================================================
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
|
|
|
|
| Line 445... |
Line 461... |
|
|
Starting Arrival
|
Starting Arrival
|
Instance Reference Type Pin Net Time Slack
|
Instance Reference Type Pin Net Time Slack
|
Clock
|
Clock
|
----------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------
|
cpu0.alu.rb_in[0] CC3_top|clk40_i FD1P3AX Q rb_in[0] 1.302 978.474
|
cpu0.alu.rb_in[0] CC3_top|clk40_i FD1P3AX Q rb_in[0] 1.296 978.937
|
cpu0.alu.rb_in[1] CC3_top|clk40_i FD1P3AX Q rb_in[1] 1.302 978.617
|
cpu0.alu.rb_in[1] CC3_top|clk40_i FD1P3AX Q rb_in[1] 1.296 979.080
|
cpu0.alu.rb_in[2] CC3_top|clk40_i FD1P3AX Q rb_in[2] 1.292 978.627
|
cpu0.alu.rb_in[2] CC3_top|clk40_i FD1P3AX Q rb_in[2] 1.284 979.092
|
cpu0.alu.rb_in[3] CC3_top|clk40_i FD1P3AX Q rb_in[3] 1.296 978.766
|
cpu0.alu.rb_in[3] CC3_top|clk40_i FD1P3AX Q rb_in[3] 1.288 979.231
|
cpu0.alu.rb_in[4] CC3_top|clk40_i FD1P3AX Q rb_in[4] 1.292 978.770
|
cpu0.alu.rb_in[4] CC3_top|clk40_i FD1P3AX Q rb_in[4] 1.284 979.235
|
cpu0.alu.ra_in[0] CC3_top|clk40_i FD1P3AX Q ra_in[0] 1.305 979.039
|
cpu0.alu.ra_in[0] CC3_top|clk40_i FD1P3AX Q ra_in[0] 1.299 979.502
|
cpu0.alu.ra_in[1] CC3_top|clk40_i FD1P3AX Q ra_in[1] 1.309 979.178
|
cpu0.alu.rb_in[5] CC3_top|clk40_i FD1P3AX Q rb_in[5] 1.284 979.533
|
cpu0.alu.ra_in[2] CC3_top|clk40_i FD1P3AX Q ra_in[2] 1.309 979.178
|
cpu0.alu.rb_in[6] CC3_top|clk40_i FD1P3AX Q rb_in[6] 1.272 979.545
|
cpu0.alu.ra_in[3] CC3_top|clk40_i FD1P3AX Q ra_in[3] 1.305 979.324
|
cpu0.alu.ra_in[1] CC3_top|clk40_i FD1P3AX Q ra_in[1] 1.299 979.645
|
cpu0.alu.ra_in[4] CC3_top|clk40_i FD1P3AX Q ra_in[4] 1.292 979.338
|
cpu0.alu.ra_in[2] CC3_top|clk40_i FD1P3AX Q ra_in[2] 1.299 979.645
|
==============================================================================================
|
==============================================================================================
|
|
|
|
|
Ending Points with Worst Slack
|
Ending Points with Worst Slack
|
******************************
|
******************************
|
|
|
Starting Required
|
Starting Required
|
Instance Reference Type Pin Net Time Slack
|
Instance Reference Type Pin Net Time Slack
|
Clock
|
Clock
|
----------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------
|
cpu0.regs.SS[14] CC3_top|clk40_i FD1P3AX D SS_s[14] 999.894 978.474
|
cpu0.regs.SS[14] CC3_top|clk40_i FD1P3AX D SS_s[14] 999.894 978.937
|
cpu0.regs.SS[15] CC3_top|clk40_i FD1P3AX D SS_s[15] 999.894 978.474
|
cpu0.regs.SS[15] CC3_top|clk40_i FD1P3AX D SS_s[15] 999.894 978.937
|
cpu0.regs.SU[14] CC3_top|clk40_i FD1P3AX D SU_s[14] 999.894 978.474
|
cpu0.regs.SU[14] CC3_top|clk40_i FD1P3AX D SU_s[14] 999.894 978.937
|
cpu0.regs.SU[15] CC3_top|clk40_i FD1P3AX D SU_s[15] 999.894 978.474
|
cpu0.regs.SU[15] CC3_top|clk40_i FD1P3AX D SU_s[15] 999.894 978.937
|
cpu0.regs.SS[12] CC3_top|clk40_i FD1P3AX D SS_s[12] 999.894 978.617
|
cpu0.regs.SS[12] CC3_top|clk40_i FD1P3AX D SS_s[12] 999.894 979.080
|
cpu0.regs.SS[13] CC3_top|clk40_i FD1P3AX D SS_s[13] 999.894 978.617
|
cpu0.regs.SS[13] CC3_top|clk40_i FD1P3AX D SS_s[13] 999.894 979.080
|
cpu0.regs.SU[12] CC3_top|clk40_i FD1P3AX D SU_s[12] 999.894 978.617
|
cpu0.regs.SU[12] CC3_top|clk40_i FD1P3AX D SU_s[12] 999.894 979.080
|
cpu0.regs.SU[13] CC3_top|clk40_i FD1P3AX D SU_s[13] 999.894 978.617
|
cpu0.regs.SU[13] CC3_top|clk40_i FD1P3AX D SU_s[13] 999.894 979.080
|
cpu0.regs.SS[10] CC3_top|clk40_i FD1P3AX D SS_s[10] 999.894 978.760
|
cpu0.regs.SS[10] CC3_top|clk40_i FD1P3AX D SS_s[10] 999.894 979.223
|
cpu0.regs.SS[11] CC3_top|clk40_i FD1P3AX D SS_s[11] 999.894 978.760
|
cpu0.regs.SS[11] CC3_top|clk40_i FD1P3AX D SS_s[11] 999.894 979.223
|
==============================================================================================
|
==============================================================================================
|
|
|
|
|
|
|
Worst Path Information
|
Worst Path Information
|
| Line 489... |
Line 505... |
Requested Period: 1000.000
|
Requested Period: 1000.000
|
- Setup time: 0.106
|
- Setup time: 0.106
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 999.894
|
= Required time: 999.894
|
|
|
- Propagation time: 21.420
|
- Propagation time: 20.957
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : 978.474
|
= Slack (critical) : 978.937
|
|
|
Number of logic level(s): 23
|
Number of logic level(s): 22
|
Starting point: cpu0.alu.rb_in[0] / Q
|
Starting point: cpu0.alu.rb_in[0] / Q
|
Ending point: cpu0.regs.SS[15] / D
|
Ending point: cpu0.regs.SS[15] / D
|
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
|
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
---------------------------------------------------------------------------------------------------------
|
-----------------------------------------------------------------------------------------------------------
|
cpu0.alu.rb_in[0] FD1P3AX Q Out 1.302 1.302 -
|
cpu0.alu.rb_in[0] FD1P3AX Q Out 1.296 1.296 -
|
rb_in[0] Net - - - - 26
|
rb_in[0] Net - - - - 24
|
cpu0.alu.alu8.a8.un8_q_out_cry_0_0_RNO INV A In 0.000 1.302 -
|
cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO INV A In 0.000 1.296 -
|
cpu0.alu.alu8.a8.un8_q_out_cry_0_0_RNO INV Z Out 0.568 1.870 -
|
cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO INV Z Out 0.568 1.864 -
|
rb_in_i[0] Net - - - - 1
|
rb_in_i[0] Net - - - - 1
|
cpu0.alu.alu8.a8.un8_q_out_cry_0_0 CCU2D A1 In 0.000 1.870 -
|
cpu0.alu.alu16.a16.un8_q_out_cry_0_0 CCU2D A1 In 0.000 1.864 -
|
cpu0.alu.alu8.a8.un8_q_out_cry_0_0 CCU2D COUT Out 1.544 3.415 -
|
cpu0.alu.alu16.a16.un8_q_out_cry_0_0 CCU2D COUT Out 1.544 3.408 -
|
un8_q_out_cry_0 Net - - - - 1
|
un8_q_out_cry_0 Net - - - - 1
|
cpu0.alu.alu8.a8.un8_q_out_cry_1_0 CCU2D CIN In 0.000 3.415 -
|
cpu0.alu.alu16.a16.un8_q_out_cry_1_0 CCU2D CIN In 0.000 3.408 -
|
cpu0.alu.alu8.a8.un8_q_out_cry_1_0 CCU2D S1 Out 1.549 4.964 -
|
cpu0.alu.alu16.a16.un8_q_out_cry_1_0 CCU2D S1 Out 1.549 4.957 -
|
un8_q_out[2] Net - - - - 1
|
un8_q_out[2] Net - - - - 1
|
cpu0.alu.alu8.a8.q_out_2_cry_1_0_RNO_0 ORCALUT4 A In 0.000 4.964 -
|
cpu0.alu.alu16.a16.q_out_2_cry_1_0_RNO_0 ORCALUT4 A In 0.000 4.957 -
|
cpu0.alu.alu8.a8.q_out_2_cry_1_0_RNO_0 ORCALUT4 Z Out 1.017 5.981 -
|
cpu0.alu.alu16.a16.q_out_2_cry_1_0_RNO_0 ORCALUT4 Z Out 1.017 5.974 -
|
q_out_2_cry_1_0_RNO_0 Net - - - - 1
|
q_out_2_cry_1_0_RNO_0 Net - - - - 1
|
cpu0.alu.alu8.a8.q_out_2_cry_1_0 CCU2D C1 In 0.000 5.981 -
|
cpu0.alu.alu16.a16.q_out_2_cry_1_0 CCU2D C1 In 0.000 5.974 -
|
cpu0.alu.alu8.a8.q_out_2_cry_1_0 CCU2D COUT Out 1.544 7.525 -
|
cpu0.alu.alu16.a16.q_out_2_cry_1_0 CCU2D COUT Out 1.544 7.519 -
|
q_out_2_cry_2 Net - - - - 1
|
q_out_2_cry_2 Net - - - - 1
|
cpu0.alu.alu8.a8.q_out_2_cry_3_0 CCU2D CIN In 0.000 7.525 -
|
cpu0.alu.alu16.a16.q_out_2_cry_3_0 CCU2D CIN In 0.000 7.519 -
|
cpu0.alu.alu8.a8.q_out_2_cry_3_0 CCU2D COUT Out 0.143 7.668 -
|
cpu0.alu.alu16.a16.q_out_2_cry_3_0 CCU2D COUT Out 0.143 7.661 -
|
q_out_2_cry_4 Net - - - - 1
|
q_out_2_cry_4 Net - - - - 1
|
cpu0.alu.alu8.a8.q_out_2_cry_5_0 CCU2D CIN In 0.000 7.668 -
|
cpu0.alu.alu16.a16.q_out_2_cry_5_0 CCU2D CIN In 0.000 7.661 -
|
cpu0.alu.alu8.a8.q_out_2_cry_5_0 CCU2D COUT Out 0.143 7.811 -
|
cpu0.alu.alu16.a16.q_out_2_cry_5_0 CCU2D COUT Out 0.143 7.804 -
|
q_out_2_cry_6 Net - - - - 1
|
q_out_2_cry_6 Net - - - - 1
|
cpu0.alu.alu8.a8.q_out_2_cry_7_0 CCU2D CIN In 0.000 7.811 -
|
cpu0.alu.alu16.a16.q_out_2_cry_7_0 CCU2D CIN In 0.000 7.804 -
|
cpu0.alu.alu8.a8.q_out_2_cry_7_0 CCU2D S0 Out 1.549 9.360 -
|
cpu0.alu.alu16.a16.q_out_2_cry_7_0 CCU2D S0 Out 1.549 9.353 -
|
N_2388 Net - - - - 1
|
N_2370 Net - - - - 1
|
cpu0.alu.alu8.a8.q_out_3[7] ORCALUT4 A In 0.000 9.360 -
|
cpu0.alu.alu16.a16.q_out_3[7] ORCALUT4 B In 0.000 9.353 -
|
cpu0.alu.alu8.a8.q_out_3[7] ORCALUT4 Z Out 1.089 10.448 -
|
cpu0.alu.alu16.a16.q_out_3[7] ORCALUT4 Z Out 1.153 10.506 -
|
arith_q[7] Net - - - - 2
|
arith_q[7] Net - - - - 3
|
cpu0.alu.alu8.q_out_4_am[7] ORCALUT4 A In 0.000 10.448 -
|
cpu0.alu.alu16.q_out_1[7] ORCALUT4 A In 0.000 10.506 -
|
cpu0.alu.alu8.q_out_4_am[7] ORCALUT4 Z Out 1.017 11.465 -
|
cpu0.alu.alu16.q_out_1[7] ORCALUT4 Z Out 1.017 11.523 -
|
q_out_4_am[7] Net - - - - 1
|
N_60 Net - - - - 1
|
cpu0.alu.alu8.q_out_4[7] PFUMX BLUT In 0.000 11.465 -
|
cpu0.alu.alu16.q_out[7] PFUMX ALUT In 0.000 11.523 -
|
cpu0.alu.alu8.q_out_4[7] PFUMX Z Out 0.286 11.751 -
|
cpu0.alu.alu16.q_out[7] PFUMX Z Out 0.286 11.809 -
|
N_160 Net - - - - 2
|
q16_out[7] Net - - - - 2
|
cpu0.alu.alu8.q_out_5_RNIRSTD1[7] ORCALUT4 A In 0.000 11.751 -
|
cpu0.alu.alu8.datamux_o_dest_bm[7] ORCALUT4 B In 0.000 11.809 -
|
cpu0.alu.alu8.q_out_5_RNIRSTD1[7] ORCALUT4 Z Out 1.089 12.840 -
|
cpu0.alu.alu8.datamux_o_dest_bm[7] ORCALUT4 Z Out 1.017 12.826 -
|
q8_out[7] Net - - - - 2
|
datamux_o_dest_bm[7] Net - - - - 1
|
cpu0.alu.q_out[7] ORCALUT4 A In 0.000 12.840 -
|
cpu0.alu.alu8.datamux_o_dest[7] PFUMX ALUT In 0.000 12.826 -
|
cpu0.alu.q_out[7] ORCALUT4 Z Out 0.449 13.289 -
|
cpu0.alu.alu8.datamux_o_dest[7] PFUMX Z Out 0.286 13.112 -
|
alu_o_result[7] Net - - - - 1
|
|
cpu0.alu.alu8.l8.datamux_o_dest[7] PFUMX ALUT In 0.000 13.289 -
|
|
cpu0.alu.alu8.l8.datamux_o_dest[7] PFUMX Z Out 0.286 13.575 -
|
|
datamux_o_dest[7] Net - - - - 2
|
datamux_o_dest[7] Net - - - - 2
|
cpu0.regs.path_left_data_RNIOEVA1[7] ORCALUT4 B In 0.000 13.575 -
|
cpu0.regs.left_1[7] ORCALUT4 A In 0.000 13.112 -
|
cpu0.regs.path_left_data_RNIOEVA1[7] ORCALUT4 Z Out 1.273 14.848 -
|
cpu0.regs.left_1[7] ORCALUT4 Z Out 1.273 14.385 -
|
left_1[7] Net - - - - 9
|
left_1[7] Net - - - - 9
|
cpu0.regs.SS_16_0[7] ORCALUT4 B In 0.000 14.848 -
|
cpu0.regs.SS_16_0[7] ORCALUT4 B In 0.000 14.385 -
|
cpu0.regs.SS_16_0[7] ORCALUT4 Z Out 1.017 15.865 -
|
cpu0.regs.SS_16_0[7] ORCALUT4 Z Out 1.017 15.402 -
|
N_250 Net - - - - 1
|
N_250 Net - - - - 1
|
cpu0.regs.SS_16[7] ORCALUT4 A In 0.000 15.865 -
|
cpu0.regs.SS_16[7] ORCALUT4 A In 0.000 15.402 -
|
cpu0.regs.SS_16[7] ORCALUT4 Z Out 1.017 16.882 -
|
cpu0.regs.SS_16[7] ORCALUT4 Z Out 1.017 16.418 -
|
SS_16[7] Net - - - - 1
|
SS_16[7] Net - - - - 1
|
cpu0.regs.SS_228_m3 ORCALUT4 B In 0.000 16.882 -
|
cpu0.regs.SS_230_m3 ORCALUT4 B In 0.000 16.418 -
|
cpu0.regs.SS_228_m3 ORCALUT4 Z Out 1.017 17.898 -
|
cpu0.regs.SS_230_m3 ORCALUT4 Z Out 1.017 17.435 -
|
SS_228_i1_mux Net - - - - 1
|
SS_230_i1_mux Net - - - - 1
|
cpu0.regs.SS_cry_0[6] CCU2D C1 In 0.000 17.898 -
|
cpu0.regs.SS_cry_0[6] CCU2D C1 In 0.000 17.435 -
|
cpu0.regs.SS_cry_0[6] CCU2D COUT Out 1.544 19.443 -
|
cpu0.regs.SS_cry_0[6] CCU2D COUT Out 1.544 18.980 -
|
SS_cry[7] Net - - - - 1
|
SS_cry[7] Net - - - - 1
|
cpu0.regs.SS_cry_0[8] CCU2D CIN In 0.000 19.443 -
|
cpu0.regs.SS_cry_0[8] CCU2D CIN In 0.000 18.980 -
|
cpu0.regs.SS_cry_0[8] CCU2D COUT Out 0.143 19.586 -
|
cpu0.regs.SS_cry_0[8] CCU2D COUT Out 0.143 19.122 -
|
SS_cry[9] Net - - - - 1
|
SS_cry[9] Net - - - - 1
|
cpu0.regs.SS_cry_0[10] CCU2D CIN In 0.000 19.586 -
|
cpu0.regs.SS_cry_0[10] CCU2D CIN In 0.000 19.122 -
|
cpu0.regs.SS_cry_0[10] CCU2D COUT Out 0.143 19.729 -
|
cpu0.regs.SS_cry_0[10] CCU2D COUT Out 0.143 19.265 -
|
SS_cry[11] Net - - - - 1
|
SS_cry[11] Net - - - - 1
|
cpu0.regs.SS_cry_0[12] CCU2D CIN In 0.000 19.729 -
|
cpu0.regs.SS_cry_0[12] CCU2D CIN In 0.000 19.265 -
|
cpu0.regs.SS_cry_0[12] CCU2D COUT Out 0.143 19.871 -
|
cpu0.regs.SS_cry_0[12] CCU2D COUT Out 0.143 19.408 -
|
SS_cry[13] Net - - - - 1
|
SS_cry[13] Net - - - - 1
|
cpu0.regs.SS_cry_0[14] CCU2D CIN In 0.000 19.871 -
|
cpu0.regs.SS_cry_0[14] CCU2D CIN In 0.000 19.408 -
|
cpu0.regs.SS_cry_0[14] CCU2D S1 Out 1.549 21.420 -
|
cpu0.regs.SS_cry_0[14] CCU2D S1 Out 1.549 20.957 -
|
SS_s[15] Net - - - - 1
|
SS_s[15] Net - - - - 1
|
cpu0.regs.SS[15] FD1P3AX D In 0.000 21.420 -
|
cpu0.regs.SS[15] FD1P3AX D In 0.000 20.957 -
|
=========================================================================================================
|
===========================================================================================================
|
|
|
|
|
|
|
##### END OF TIMING REPORT #####]
|
##### END OF TIMING REPORT #####]
|
|
|
---------------------------------------
|
---------------------------------------
|
Resource Usage Report
|
Resource Usage Report
|
Part: lcmxo2_7000he-4
|
Part: lcmxo2_7000he-4
|
|
|
Register bits: 439 of 6864 (6%)
|
Register bits: 580 of 6864 (8%)
|
PIC Latch: 0
|
PIC Latch: 0
|
I/O cells: 49
|
I/O cells: 69
|
Block Rams : 10 of 26 (38%)
|
Block Rams : 10 of 26 (38%)
|
|
|
|
|
Details:
|
Details:
|
CCU2D: 196
|
BB: 8
|
|
CCU2D: 186
|
DP8KC: 10
|
DP8KC: 10
|
FD1P3AX: 393
|
FD1P3AX: 529
|
FD1P3DX: 6
|
FD1P3DX: 6
|
FD1S3AX: 28
|
FD1S3AX: 32
|
FD1S3IX: 2
|
FD1S3IX: 3
|
GSR: 1
|
GSR: 1
|
IB: 1
|
IB: 1
|
INV: 19
|
INV: 20
|
L6MUX21: 26
|
L6MUX21: 16
|
OB: 40
|
OB: 60
|
OBZ: 8
|
|
OFS1P3DX: 9
|
OFS1P3DX: 9
|
OFS1P3IX: 1
|
OFS1P3IX: 1
|
ORCALUT4: 2024
|
ORCALUT4: 2014
|
PFUMX: 222
|
PFUMX: 226
|
PUR: 1
|
PUR: 1
|
VHI: 13
|
VHI: 14
|
VLO: 20
|
VLO: 20
|
false: 1
|
false: 1
|
true: 8
|
true: 7
|
Mapper successful!
|
Mapper successful!
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 44MB peak: 229MB)
|
At Mapper Exit (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:17s; Memory used current: 44MB peak: 230MB)
|
|
|
Process took 0h:00m:14s realtime, 0h:00m:14s cputime
|
Process took 0h:00m:30s realtime, 0h:00m:17s cputime
|
# Mon Jan 6 06:54:29 2014
|
# Thu Feb 6 15:35:11 2014
|
|
|
###########################################################]
|
###########################################################]
|
