| Line 13... |
Line 13... |
textctrl/font/VCC
|
textctrl/font/VCC
|
textctrl/font/GND
|
textctrl/font/GND
|
textctrl/chars/VCC
|
textctrl/chars/VCC
|
textctrl/chars/GND
|
textctrl/chars/GND
|
VCC
|
VCC
|
GND
|
|
cpu0/un1_k_cpu_addr_1_s_15_0_S1
|
cpu0/un1_k_cpu_addr_1_s_15_0_S1
|
cpu0/un1_k_cpu_addr_1_s_15_0_COUT
|
cpu0/un1_k_cpu_addr_1_s_15_0_COUT
|
|
cpu0/un1_regs_o_pc_cry_0_0_S1
|
|
cpu0/un1_regs_o_pc_cry_0_0_S0
|
|
cpu0/N_2
|
|
cpu0/un1_regs_o_pc_s_15_0_S1
|
|
cpu0/un1_regs_o_pc_s_15_0_COUT
|
cpu0/alu/alu8/neg8_w_cry_0_0_S1
|
cpu0/alu/alu8/neg8_w_cry_0_0_S1
|
cpu0/alu/alu8/neg8_w_cry_0_0_S0
|
cpu0/alu/alu8/neg8_w_cry_0_0_S0
|
cpu0/alu/alu8/N_1
|
cpu0/alu/alu8/N_1
|
cpu0/alu/alu8/neg8_w_s_7_0_S1
|
cpu0/alu/alu8/neg8_w_s_7_0_S1
|
cpu0/alu/alu8/neg8_w_s_7_0_COUT
|
cpu0/alu/alu8/neg8_w_s_7_0_COUT
|
cpu0/alu/alu8/a8/q_out_1_0_cry_0_S0_0
|
cpu0/alu/alu8/a8/q_out_1_cry_0_0_S0_0
|
cpu0/alu/alu8/a8/N_1
|
cpu0/alu/alu8/a8/N_1
|
cpu0/alu/alu8/a8/q_out_1_0_cry_7_0_COUT
|
|
cpu0/alu/alu8/a8/q_out_2_cry_0_0_S0_0
|
|
cpu0/alu/alu8/a8/N_2
|
|
cpu0/alu/alu8/a8/q_out_2_cry_7_0_COUT
|
|
cpu0/alu/alu8/a8/q_out_1_cry_0_0_S1
|
|
cpu0/alu/alu8/a8/q_out_1_cry_0_0_S0
|
|
cpu0/alu/alu8/a8/N_3
|
|
cpu0/alu/alu8/a8/q_out_1_cry_7_0_COUT
|
cpu0/alu/alu8/a8/q_out_1_cry_7_0_COUT
|
cpu0/alu/alu8/a8/un8_q_out_cry_0_0_S1
|
cpu0/alu/alu8/a8/un9_q_out_cry_0_0_S1
|
cpu0/alu/alu8/a8/un8_q_out_cry_0_0_S0
|
cpu0/alu/alu8/a8/un9_q_out_cry_0_0_S0
|
cpu0/alu/alu8/a8/N_4
|
cpu0/alu/alu8/a8/N_2
|
cpu0/alu/alu8/a8/un8_q_out_cry_7_0_COUT
|
cpu0/alu/alu8/a8/un9_q_out_cry_7_0_COUT
|
cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S1
|
cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S1
|
cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S0
|
cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S0
|
cpu0/alu/alu16/mulu/N_1
|
cpu0/alu/alu16/mulu/N_1
|
cpu0/alu/alu16/mulu/pipe0_1_s_11_0_S1
|
cpu0/alu/alu16/mulu/pipe0_1_s_11_0_S1
|
cpu0/alu/alu16/mulu/pipe0_1_s_11_0_COUT
|
cpu0/alu/alu16/mulu/pipe0_1_s_11_0_COUT
|
| Line 62... |
Line 59... |
cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S1
|
cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S1
|
cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S0
|
cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S0
|
cpu0/alu/alu16/mulu/N_6
|
cpu0/alu/alu16/mulu/N_6
|
cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_S1
|
cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_S1
|
cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_COUT
|
cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_COUT
|
cpu0/alu/alu16/a16/q_out_1_0_cry_0_0_S0
|
|
cpu0/alu/alu16/a16/N_1
|
|
cpu0/alu/alu16/a16/q_out_1_0_cry_15_0_COUT
|
|
cpu0/alu/alu16/a16/q_out_2_cry_0_0_S0
|
cpu0/alu/alu16/a16/q_out_2_cry_0_0_S0
|
cpu0/alu/alu16/a16/N_2
|
cpu0/alu/alu16/a16/N_1
|
cpu0/alu/alu16/a16/q_out_2_cry_15_0_COUT
|
cpu0/alu/alu16/a16/q_out_2_cry_15_0_COUT
|
cpu0/alu/alu16/a16/q_out_1_cry_0_0_S1_0
|
cpu0/alu/alu16/a16/q_out_1_0_cry_0_0_S0
|
cpu0/alu/alu16/a16/q_out_1_cry_0_0_S0_0
|
cpu0/alu/alu16/a16/N_2
|
|
cpu0/alu/alu16/a16/q_out_1_0_cry_15_0_COUT
|
|
cpu0/alu/alu16/a16/un8_q_out_cry_0_0_S1
|
|
cpu0/alu/alu16/a16/un8_q_out_cry_0_0_S0
|
cpu0/alu/alu16/a16/N_3
|
cpu0/alu/alu16/a16/N_3
|
cpu0/alu/alu16/a16/q_out_1_cry_15_0_COUT
|
|
cpu0/alu/alu16/a16/un8_q_out_cry_0_0_S1_0
|
|
cpu0/alu/alu16/a16/un8_q_out_cry_0_0_S0_0
|
|
cpu0/alu/alu16/a16/N_4
|
|
cpu0/alu/alu16/a16/un8_q_out_cry_15_0_COUT
|
cpu0/alu/alu16/a16/un8_q_out_cry_15_0_COUT
|
|
cpu0/alu/alu16/a16/q_out_1_cry_0_0_S1
|
|
cpu0/alu/alu16/a16/q_out_1_cry_0_0_S0
|
|
cpu0/alu/alu16/a16/N_4
|
|
cpu0/alu/alu16/a16/q_out_1_cry_15_0_COUT
|
cpu0/regs/right_cry_0_0_S0
|
cpu0/regs/right_cry_0_0_S0
|
cpu0/regs/N_1
|
cpu0/regs/N_1
|
cpu0/regs/right_s_15_0_S1
|
cpu0/regs/right_s_15_0_S1
|
cpu0/regs/right_s_15_0_COUT
|
cpu0/regs/right_s_15_0_COUT
|
cpu0/regs/SS_lcry_0_S1
|
cpu0/regs/SS_lcry_0_S1
|
| Line 88... |
Line 85... |
cpu0/regs/SS_cry_0_COUT[14]
|
cpu0/regs/SS_cry_0_COUT[14]
|
cpu0/regs/SU_lcry_0_S1
|
cpu0/regs/SU_lcry_0_S1
|
cpu0/regs/SU_lcry_0_S0
|
cpu0/regs/SU_lcry_0_S0
|
cpu0/regs/N_3
|
cpu0/regs/N_3
|
cpu0/regs/SU_cry_0_COUT[14]
|
cpu0/regs/SU_cry_0_COUT[14]
|
cpu0/regs/ea/k_new_pc_4_cry_0_0_S1
|
|
cpu0/regs/ea/k_new_pc_4_cry_0_0_S0
|
|
cpu0/regs/ea/N_1
|
|
cpu0/regs/ea/k_new_pc_4_s_15_0_S1
|
|
cpu0/regs/ea/k_new_pc_4_s_15_0_COUT
|
|
cpu0/regs/ea/ea_reg_post_o_cry_0_0_S1
|
cpu0/regs/ea/ea_reg_post_o_cry_0_0_S1
|
cpu0/regs/ea/ea_reg_post_o_cry_0_0_S0
|
cpu0/regs/ea/ea_reg_post_o_cry_0_0_S0
|
cpu0/regs/ea/N_2
|
cpu0/regs/ea/N_1
|
cpu0/regs/ea/ea_reg_post_o_s_15_0_S1
|
cpu0/regs/ea/ea_reg_post_o_s_15_0_S1
|
cpu0/regs/ea/ea_reg_post_o_s_15_0_COUT
|
cpu0/regs/ea/ea_reg_post_o_s_15_0_COUT
|
cpu0/regs/ea/eamem_addr_o_cry_0_0_S1
|
cpu0/regs/ea/eamem_addr_o_cry_0_0_S1
|
cpu0/regs/ea/eamem_addr_o_cry_0_0_S0
|
cpu0/regs/ea/eamem_addr_o_cry_0_0_S0
|
cpu0/regs/ea/N_3
|
cpu0/regs/ea/N_2
|
cpu0/regs/ea/eamem_addr_o_s_15_0_S1
|
cpu0/regs/ea/eamem_addr_o_s_15_0_S1
|
cpu0/regs/ea/eamem_addr_o_s_15_0_COUT
|
cpu0/regs/ea/eamem_addr_o_s_15_0_COUT
|
cpu0/un1_k_cpu_addr_1_cry_0_0_S1
|
cpu0/un1_k_cpu_addr_1_cry_0_0_S1
|
cpu0/un1_k_cpu_addr_1_cry_0_0_S0
|
cpu0/un1_k_cpu_addr_1_cry_0_0_S0
|
cpu0/N_1
|
cpu0/N_1
|
| Line 286... |
Line 278... |
textctrl/chars/textmem4k_0_0_3_DOA3
|
textctrl/chars/textmem4k_0_0_3_DOA3
|
textctrl/chars/textmem4k_0_0_3_DOA2
|
textctrl/chars/textmem4k_0_0_3_DOA2
|
[ END CLIPPED ]
|
[ END CLIPPED ]
|
[ START DESIGN PREFS ]
|
[ START DESIGN PREFS ]
|
SCHEMATIC START ;
|
SCHEMATIC START ;
|
# map: version Diamond (64-bit) 2.2.0.101 -- WARNING: Map write only section -- Mon Jan 6 06:54:32 2014
|
# map: version Diamond (64-bit) 2.2.0.101 -- WARNING: Map write only section -- Thu Feb 6 15:35:20 2014
|
|
|
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE ;
|
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE ;
|
LOCATE COMP "data_io[0]" SITE "143" ;
|
LOCATE COMP "data_io[0]" SITE "132" ;
|
LOCATE COMP "cpuclk_o" SITE "60" ;
|
|
LOCATE COMP "clk40_i" SITE "27" ;
|
LOCATE COMP "clk40_i" SITE "27" ;
|
|
LOCATE COMP "ldata_io[7]" SITE "10" ;
|
|
LOCATE COMP "ldata_io[6]" SITE "9" ;
|
|
LOCATE COMP "ldata_io[5]" SITE "6" ;
|
|
LOCATE COMP "ldata_io[4]" SITE "5" ;
|
|
LOCATE COMP "ldata_io[3]" SITE "4" ;
|
|
LOCATE COMP "ldata_io[2]" SITE "3" ;
|
|
LOCATE COMP "ldata_io[1]" SITE "2" ;
|
|
LOCATE COMP "ldata_io[0]" SITE "1" ;
|
|
LOCATE COMP "lcen_o" SITE "23" ;
|
|
LOCATE COMP "lwen_o" SITE "24" ;
|
|
LOCATE COMP "loen_o" SITE "25" ;
|
|
LOCATE COMP "laddr_o[5]" SITE "20" ;
|
|
LOCATE COMP "laddr_o[4]" SITE "19" ;
|
|
LOCATE COMP "laddr_o[3]" SITE "14" ;
|
|
LOCATE COMP "laddr_o[2]" SITE "13" ;
|
|
LOCATE COMP "laddr_o[1]" SITE "12" ;
|
|
LOCATE COMP "laddr_o[0]" SITE "11" ;
|
LOCATE COMP "blue_o" SITE "74" ;
|
LOCATE COMP "blue_o" SITE "74" ;
|
LOCATE COMP "green_o" SITE "76" ;
|
LOCATE COMP "green_o" SITE "76" ;
|
LOCATE COMP "red_o" SITE "78" ;
|
LOCATE COMP "red_o" SITE "78" ;
|
LOCATE COMP "vsync_o" SITE "75" ;
|
LOCATE COMP "vsync_o" SITE "75" ;
|
LOCATE COMP "hsync_o" SITE "73" ;
|
LOCATE COMP "hsync_o" SITE "73" ;
|
| Line 305... |
Line 313... |
LOCATE COMP "leds_o[4]" SITE "104" ;
|
LOCATE COMP "leds_o[4]" SITE "104" ;
|
LOCATE COMP "leds_o[3]" SITE "100" ;
|
LOCATE COMP "leds_o[3]" SITE "100" ;
|
LOCATE COMP "leds_o[2]" SITE "99" ;
|
LOCATE COMP "leds_o[2]" SITE "99" ;
|
LOCATE COMP "leds_o[1]" SITE "98" ;
|
LOCATE COMP "leds_o[1]" SITE "98" ;
|
LOCATE COMP "leds_o[0]" SITE "97" ;
|
LOCATE COMP "leds_o[0]" SITE "97" ;
|
LOCATE COMP "state_o[5]" SITE "62" ;
|
LOCATE COMP "state_o[5]" SITE "35" ;
|
LOCATE COMP "state_o[4]" SITE "65" ;
|
LOCATE COMP "state_o[4]" SITE "34" ;
|
LOCATE COMP "state_o[3]" SITE "61" ;
|
LOCATE COMP "state_o[3]" SITE "33" ;
|
LOCATE COMP "state_o[2]" SITE "126" ;
|
LOCATE COMP "state_o[2]" SITE "32" ;
|
LOCATE COMP "state_o[1]" SITE "127" ;
|
LOCATE COMP "state_o[1]" SITE "28" ;
|
LOCATE COMP "state_o[0]" SITE "128" ;
|
LOCATE COMP "state_o[0]" SITE "26" ;
|
LOCATE COMP "data_io[7]" SITE "132" ;
|
LOCATE COMP "data_io[7]" SITE "133" ;
|
LOCATE COMP "data_io[6]" SITE "133" ;
|
LOCATE COMP "data_io[6]" SITE "139" ;
|
LOCATE COMP "data_io[5]" SITE "138" ;
|
LOCATE COMP "data_io[5]" SITE "141" ;
|
LOCATE COMP "data_io[4]" SITE "139" ;
|
LOCATE COMP "data_io[4]" SITE "143" ;
|
LOCATE COMP "data_io[3]" SITE "140" ;
|
LOCATE COMP "data_io[3]" SITE "142" ;
|
LOCATE COMP "data_io[2]" SITE "141" ;
|
LOCATE COMP "data_io[2]" SITE "140" ;
|
LOCATE COMP "data_io[1]" SITE "142" ;
|
LOCATE COMP "data_io[1]" SITE "138" ;
|
LOCATE COMP "cen_o" SITE "57" ;
|
LOCATE COMP "cen_o" SITE "48" ;
|
LOCATE COMP "wen_o" SITE "59" ;
|
LOCATE COMP "wen_o" SITE "112" ;
|
LOCATE COMP "oen_o" SITE "58" ;
|
LOCATE COMP "oen_o" SITE "54" ;
|
LOCATE COMP "addr_o[15]" SITE "56" ;
|
LOCATE COMP "addr_o[18]" SITE "69" ;
|
LOCATE COMP "addr_o[14]" SITE "54" ;
|
LOCATE COMP "addr_o[17]" SITE "109" ;
|
LOCATE COMP "addr_o[13]" SITE "55" ;
|
LOCATE COMP "addr_o[16]" SITE "71" ;
|
LOCATE COMP "addr_o[12]" SITE "52" ;
|
LOCATE COMP "addr_o[15]" SITE "110" ;
|
LOCATE COMP "addr_o[11]" SITE "50" ;
|
LOCATE COMP "addr_o[14]" SITE "70" ;
|
LOCATE COMP "addr_o[10]" SITE "48" ;
|
LOCATE COMP "addr_o[13]" SITE "62" ;
|
LOCATE COMP "addr_o[9]" SITE "49" ;
|
LOCATE COMP "addr_o[12]" SITE "67" ;
|
LOCATE COMP "addr_o[8]" SITE "47" ;
|
LOCATE COMP "addr_o[11]" SITE "57" ;
|
LOCATE COMP "addr_o[7]" SITE "45" ;
|
LOCATE COMP "addr_o[10]" SITE "52" ;
|
LOCATE COMP "addr_o[6]" SITE "43" ;
|
LOCATE COMP "addr_o[9]" SITE "58" ;
|
LOCATE COMP "addr_o[5]" SITE "44" ;
|
LOCATE COMP "addr_o[8]" SITE "61" ;
|
LOCATE COMP "addr_o[4]" SITE "42" ;
|
LOCATE COMP "addr_o[7]" SITE "65" ;
|
LOCATE COMP "addr_o[3]" SITE "41" ;
|
LOCATE COMP "addr_o[6]" SITE "60" ;
|
LOCATE COMP "addr_o[2]" SITE "39" ;
|
LOCATE COMP "addr_o[5]" SITE "59" ;
|
LOCATE COMP "addr_o[1]" SITE "40" ;
|
LOCATE COMP "addr_o[4]" SITE "56" ;
|
LOCATE COMP "addr_o[0]" SITE "38" ;
|
LOCATE COMP "addr_o[3]" SITE "55" ;
|
LOCATE COMP "reset_o" SITE "125" ;
|
LOCATE COMP "addr_o[2]" SITE "50" ;
|
|
LOCATE COMP "addr_o[1]" SITE "49" ;
|
|
LOCATE COMP "addr_o[0]" SITE "45" ;
|
|
LOCATE COMP "reset_o" SITE "22" ;
|
FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
SCHEMATIC END ;
|
SCHEMATIC END ;
|
[ END DESIGN PREFS ]
|
[ END DESIGN PREFS ]
|
