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Line 41... |
set_option -update_models_cp 0
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set_option -update_models_cp 0
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set_option -resolve_multiple_driver 0
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set_option -resolve_multiple_driver 0
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#-- add_file options
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#-- add_file options
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set_option -include_path {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice}
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set_option -include_path {C:/02_Elektronik/020_V6809/trunk/syn/lattice}
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add_file -verilog {/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/CC3_top.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/defs.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/MC6809_cpu.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/regblock.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/bios2k.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/vgatext.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/fontrom.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v}
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add_file -verilog {C:/02_Elektronik/020_V6809/trunk/syn/lattice/textmem4k.v}
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add_file -verilog {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v}
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#-- top module name
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#-- top module name
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set_option -top_module CC3_top
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set_option -top_module CC3_top
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#-- set result format/file last
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#-- set result format/file last
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project -result_file {/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi}
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project -result_file {C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809/P6809_P6809.edi}
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#-- error message log file
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#-- error message log file
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project -log_file {P6809_P6809.srf}
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project -log_file {P6809_P6809.srf}
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#-- set any command lines input by customer
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#-- set any command lines input by customer
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