URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809_tw1.html] - Diff between revs 9 and 10

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Rev 9	Rev 10
Line 20...	Line 20...
`Performance Hardware Data Status: Final) Version 23.4`	`Performance Hardware Data Status: Final) Version 23.4`
`Setup and Hold Report`	`Setup and Hold Report`

`--------------------------------------------------------------------------------`	`--------------------------------------------------------------------------------`
`<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101</big></U></B>`	`<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101</big></U></B>`
`Mon Jan 6 06:54:33 2014`	`Thu Feb 6 15:35:22 2014`

`Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.`	`Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.`
`Copyright (c) 1995 AT&T Corp. All rights reserved.`	`Copyright (c) 1995 AT&T Corp. All rights reserved.`
`Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.`	`Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.`
`Copyright (c) 2001 Agere Systems All rights reserved.`	`Copyright (c) 2001 Agere Systems All rights reserved.`
Line 39...	Line 39...
`Report level: verbose report, limited to 1 item per preference`	`Report level: verbose report, limited to 1 item per preference`
`--------------------------------------------------------------------------------`	`--------------------------------------------------------------------------------`

`<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>`	`<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>`

`<FONT COLOR=red><LI><A href='#map_twr_pref_0_0' Target='right'><FONT COLOR=red>FREQUENCY NET "cpu_clkgen" 40.000000 MHz (672 errors)</FONT></A></LI>`	`<FONT COLOR=red><LI><A href='#map_twr_pref_0_0' Target='right'><FONT COLOR=red>FREQUENCY NET "cpu_clkgen" 40.000000 MHz (198 errors)</FONT></A></LI>`
`</FONT> 4096 items scored, 672 timing errors detected.`	`</FONT> 4096 items scored, 198 timing errors detected.`
`Warning: 37.396MHz is the maximum frequency for this preference.`	`Warning: 39.118MHz is the maximum frequency for this preference.`

`BLOCK ASYNCPATHS`	`BLOCK ASYNCPATHS`
`BLOCK RESETPATHS`	`BLOCK RESETPATHS`
`--------------------------------------------------------------------------------`	`--------------------------------------------------------------------------------`



`================================================================================`	`================================================================================`
`<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;`	`<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;`
`4096 items scored, 672 timing errors detected.`	`4096 items scored, 198 timing errors detected.`
`--------------------------------------------------------------------------------`	`--------------------------------------------------------------------------------`


`Error: The following path exceeds requirements by 1.741ns`	`Error: The following path exceeds requirements by 0.564ns`

`Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)`	`Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)`

`Source: FF Q cpu0/alu/rb_in[0] (from cpu_clkgen +)`	`Source: FF Q cpu0/alu/rb_in[0] (from cpu_clkgen +)`
`Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)`	`Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)`

`Delay: 26.575ns (42.4% logic, 57.6% route), 22 logic levels.`	`Delay: 25.398ns (42.7% logic, 57.3% route), 21 logic levels.`

`Constraint Details:`	`Constraint Details:`

`26.575ns physical path delay cpu0/SLICE_229 to cpu0/regs/SLICE_64 exceeds`	`25.398ns physical path delay cpu0/alu/SLICE_215 to cpu0/regs/SLICE_55 exceeds`
`25.000ns delay constraint less`	`25.000ns delay constraint less`
`0.166ns DIN_SET requirement (totaling 24.834ns) by 1.741ns`	`0.166ns DIN_SET requirement (totaling 24.834ns) by 0.564ns`

`Physical Path Details:`	`Physical Path Details:`

`Data path cpu0/SLICE_229 to cpu0/regs/SLICE_64:`	`Data path cpu0/alu/SLICE_215 to cpu0/regs/SLICE_55:`

`Name Fanout Delay (ns) Site Resource`	`Name Fanout Delay (ns) Site Resource`
`REG_DEL --- 0.452 SLICE_229.CLK to /SLICE_229.Q0 cpu0/SLICE_229 (from cpu_clkgen)`	`REG_DEL --- 0.452 SLICE_215.CLK to /SLICE_215.Q0 cpu0/alu/SLICE_215 (from cpu_clkgen)`
`ROUTE 26 e 1.234 /SLICE_229.Q0 to SLICE_1227.A1 cpu0/alu/rb_in[0]`	`ROUTE 24 e 1.234 /SLICE_215.Q0 to /SLICE_199.A1 cpu0/alu/rb_in[0]`
`CTOF_DEL --- 0.495 SLICE_1227.A1 to SLICE_1227.F1 cpu0/alu/SLICE_1227`	`CTOF_DEL --- 0.495 /SLICE_199.A1 to /SLICE_199.F1 cpu0/alu/alu16/SLICE_199`
`ROUTE 1 e 1.234 SLICE_1227.F1 to /SLICE_167.A1 cpu0/alu/alu8/a8/rb_in_i[0]`	`ROUTE 1 e 1.234 /SLICE_199.F1 to 6/SLICE_99.A1 cpu0/alu/alu16/a16/rb_in_i[0]`
`C1TOFCO_DE --- 0.889 /SLICE_167.A1 to SLICE_167.FCO cpu0/alu/alu8/a8/SLICE_167`	`C1TOFCO_DE --- 0.889 6/SLICE_99.A1 to /SLICE_99.FCO cpu0/alu/alu16/a16/SLICE_99`
`ROUTE 1 e 0.001 SLICE_167.FCO to SLICE_166.FCI cpu0/alu/alu8/a8/un8_q_out_cry_0`	`ROUTE 1 e 0.001 /SLICE_99.FCO to /SLICE_98.FCI cpu0/alu/alu16/a16/un8_q_out_cry_0`
`FCITOF0_DE --- 0.585 SLICE_166.FCI to /SLICE_166.F0 cpu0/alu/alu8/a8/SLICE_166`	`FCITOF0_DE --- 0.585 /SLICE_98.FCI to 6/SLICE_98.F0 cpu0/alu/alu16/a16/SLICE_98`
`ROUTE 1 e 1.234 /SLICE_166.F0 to SLICE_1216.A1 cpu0/alu/alu8/a8/un8_q_out[1]`	`ROUTE 1 e 1.234 6/SLICE_98.F0 to SLICE_1214.A0 cpu0/alu/alu16/a16/un8_q_out[1]`
`CTOF_DEL --- 0.495 SLICE_1216.A1 to SLICE_1216.F1 cpu0/alu/SLICE_1216`	`CTOF_DEL --- 0.495 SLICE_1214.A0 to SLICE_1214.F0 cpu0/alu/SLICE_1214`
`ROUTE 1 e 1.234 SLICE_1216.F1 to /SLICE_176.C0 cpu0/alu/alu8/a8/q_out_2_cry_1_0_RNO`	`ROUTE 1 e 1.234 SLICE_1214.F0 to /SLICE_116.C0 cpu0/alu/alu16/a16/q_out_2_cry_1_0_RNO`
`C0TOFCO_DE --- 1.023 /SLICE_176.C0 to SLICE_176.FCO cpu0/alu/alu8/a8/SLICE_176`	`C0TOFCO_DE --- 1.023 /SLICE_116.C0 to SLICE_116.FCO cpu0/alu/alu16/a16/SLICE_116`
`ROUTE 1 e 0.001 SLICE_176.FCO to SLICE_175.FCI cpu0/alu/alu8/a8/q_out_2_cry_2`	`ROUTE 1 e 0.001 SLICE_116.FCO to SLICE_115.FCI cpu0/alu/alu16/a16/q_out_2_cry_2`
`FCITOFCO_D --- 0.162 SLICE_175.FCI to SLICE_175.FCO cpu0/alu/alu8/a8/SLICE_175`	`FCITOFCO_D --- 0.162 SLICE_115.FCI to SLICE_115.FCO cpu0/alu/alu16/a16/SLICE_115`
`ROUTE 1 e 0.001 SLICE_175.FCO to SLICE_174.FCI cpu0/alu/alu8/a8/q_out_2_cry_4`	`ROUTE 1 e 0.001 SLICE_115.FCO to SLICE_114.FCI cpu0/alu/alu16/a16/q_out_2_cry_4`
`FCITOFCO_D --- 0.162 SLICE_174.FCI to SLICE_174.FCO cpu0/alu/alu8/a8/SLICE_174`	`FCITOFCO_D --- 0.162 SLICE_114.FCI to SLICE_114.FCO cpu0/alu/alu16/a16/SLICE_114`
`ROUTE 1 e 0.001 SLICE_174.FCO to SLICE_173.FCI cpu0/alu/alu8/a8/q_out_2_cry_6`	`ROUTE 1 e 0.001 SLICE_114.FCO to SLICE_113.FCI cpu0/alu/alu16/a16/q_out_2_cry_6`
`FCITOF0_DE --- 0.585 SLICE_173.FCI to /SLICE_173.F0 cpu0/alu/alu8/a8/SLICE_173`	`FCITOFCO_D --- 0.162 SLICE_113.FCI to SLICE_113.FCO cpu0/alu/alu16/a16/SLICE_113`
`ROUTE 1 e 1.234 /SLICE_173.F0 to /SLICE_639.A1 cpu0/alu/alu8/a8/N_2388`	`ROUTE 1 e 0.001 SLICE_113.FCO to SLICE_112.FCI cpu0/alu/alu16/a16/q_out_2_cry_8`
`CTOF_DEL --- 0.495 /SLICE_639.A1 to /SLICE_639.F1 cpu0/alu/alu8/a8/SLICE_639`	`FCITOFCO_D --- 0.162 SLICE_112.FCI to SLICE_112.FCO cpu0/alu/alu16/a16/SLICE_112`
`ROUTE 2 e 1.234 /SLICE_639.F1 to /SLICE_561.A0 cpu0/alu/alu8/arith_q[7]`	`ROUTE 1 e 0.001 SLICE_112.FCO to SLICE_111.FCI cpu0/alu/alu16/a16/q_out_2_cry_10`
`CTOOFX_DEL --- 0.721 /SLICE_561.A0 to LICE_561.OFX0 cpu0/alu/alu8/q_out_4[7]/SLICE_561`	`FCITOF1_DE --- 0.643 SLICE_111.FCI to /SLICE_111.F1 cpu0/alu/alu16/a16/SLICE_111`
`ROUTE 2 e 1.234 LICE_561.OFX0 to SLICE_1235.A0 cpu0/alu/alu8/N_160`	`ROUTE 1 e 1.234 /SLICE_111.F1 to SLICE_1048.B0 cpu0/alu/alu16/a16/N_2375`
`CTOF_DEL --- 0.495 SLICE_1235.A0 to SLICE_1235.F0 cpu0/alu/alu8/SLICE_1235`	`CTOF_DEL --- 0.495 SLICE_1048.B0 to SLICE_1048.F0 cpu0/alu/alu16/SLICE_1048`
`ROUTE 2 e 1.234 SLICE_1235.F0 to /SLICE_542.A1 cpu0/alu/q8_out[7]`	`ROUTE 1 e 0.480 SLICE_1048.F0 to SLICE_1048.A1 cpu0/alu/alu16/arith_q[12]`
`CTOOFX_DEL --- 0.721 /SLICE_542.A1 to LICE_542.OFX0 cpu0/alu/alu8/l8/datamux_o_dest[7]/SLICE_542`	`CTOF_DEL --- 0.495 SLICE_1048.A1 to SLICE_1048.F1 cpu0/alu/alu16/SLICE_1048`
`ROUTE 2 e 1.234 LICE_542.OFX0 to /SLICE_361.B1 cpu0/datamux_o_dest[7]`	`ROUTE 1 e 1.234 SLICE_1048.F1 to SLICE_1066.A1 cpu0/alu/alu16/N_2342`
`CTOF_DEL --- 0.495 /SLICE_361.B1 to /SLICE_361.F1 cpu0/regs/SLICE_361`	`CTOF_DEL --- 0.495 SLICE_1066.A1 to SLICE_1066.F1 cpu0/alu/alu16/SLICE_1066`
`ROUTE 9 e 1.234 /SLICE_361.F1 to SLICE_1126.B0 cpu0/regs/left_1[7]`	`ROUTE 2 e 1.234 SLICE_1066.F1 to SLICE_1082.B0 cpu0/alu/q16_out[12]`
`CTOF_DEL --- 0.495 SLICE_1126.B0 to SLICE_1126.F0 cpu0/regs/SLICE_1126`	`CTOF_DEL --- 0.495 SLICE_1082.B0 to SLICE_1082.F0 cpu0/alu/SLICE_1082`
`ROUTE 1 e 1.234 SLICE_1126.F0 to /SLICE_902.A1 cpu0/regs/N_286`	`ROUTE 2 e 1.234 SLICE_1082.F0 to /SLICE_363.A0 cpu0/datamux_o_dest[12]`
`CTOF_DEL --- 0.495 /SLICE_902.A1 to /SLICE_902.F1 cpu0/regs/SLICE_902`	`CTOF_DEL --- 0.495 /SLICE_363.A0 to /SLICE_363.F0 cpu0/regs/SLICE_363`
`ROUTE 1 e 0.480 /SLICE_902.F1 to /SLICE_902.B0 cpu0/regs/SU_16[7]`	`ROUTE 6 e 1.234 /SLICE_363.F0 to SLICE_1193.B0 cpu0/regs/left_1[12]`
`CTOF_DEL --- 0.495 /SLICE_902.B0 to /SLICE_902.F0 cpu0/regs/SLICE_902`	`CTOF_DEL --- 0.495 SLICE_1193.B0 to SLICE_1193.F0 cpu0/regs/SLICE_1193`
`ROUTE 1 e 1.234 /SLICE_902.F0 to s/SLICE_68.C1 cpu0/regs/SU_212_i1_mux`	`ROUTE 1 e 1.234 SLICE_1193.F0 to /SLICE_951.A1 cpu0/regs/N_291`
`C1TOFCO_DE --- 0.889 s/SLICE_68.C1 to /SLICE_68.FCO cpu0/regs/SLICE_68`	`CTOF_DEL --- 0.495 /SLICE_951.A1 to /SLICE_951.F1 cpu0/regs/SLICE_951`
`ROUTE 1 e 0.001 /SLICE_68.FCO to /SLICE_67.FCI cpu0/regs/SU_cry[7]`	`ROUTE 1 e 0.480 /SLICE_951.F1 to /SLICE_951.B0 cpu0/regs/SU_16[12]`
`FCITOFCO_D --- 0.162 /SLICE_67.FCI to /SLICE_67.FCO cpu0/regs/SLICE_67`	`CTOF_DEL --- 0.495 /SLICE_951.B0 to /SLICE_951.F0 cpu0/regs/SLICE_951`
`ROUTE 1 e 0.001 /SLICE_67.FCO to /SLICE_66.FCI cpu0/regs/SU_cry[9]`	`ROUTE 1 e 1.234 /SLICE_951.F0 to s/SLICE_56.C0 cpu0/regs/SU_219_i1_mux`
`FCITOFCO_D --- 0.162 /SLICE_66.FCI to /SLICE_66.FCO cpu0/regs/SLICE_66`	`C0TOFCO_DE --- 1.023 s/SLICE_56.C0 to /SLICE_56.FCO cpu0/regs/SLICE_56`
`ROUTE 1 e 0.001 /SLICE_66.FCO to /SLICE_65.FCI cpu0/regs/SU_cry[11]`	`ROUTE 1 e 0.001 /SLICE_56.FCO to /SLICE_55.FCI cpu0/regs/SU_cry[13]`
`FCITOFCO_D --- 0.162 /SLICE_65.FCI to /SLICE_65.FCO cpu0/regs/SLICE_65`	`FCITOF1_DE --- 0.643 /SLICE_55.FCI to s/SLICE_55.F1 cpu0/regs/SLICE_55`
`ROUTE 1 e 0.001 /SLICE_65.FCO to /SLICE_64.FCI cpu0/regs/SU_cry[13]`	`ROUTE 1 e 0.001 s/SLICE_55.F1 to /SLICE_55.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)`
`FCITOF1_DE --- 0.643 /SLICE_64.FCI to s/SLICE_64.F1 cpu0/regs/SLICE_64`
`ROUTE 1 e 0.001 s/SLICE_64.F1 to /SLICE_64.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)`
`--------`	`--------`
`26.575 (42.4% logic, 57.6% route), 22 logic levels.`	`25.398 (42.7% logic, 57.3% route), 21 logic levels.`

`Warning: 37.396MHz is the maximum frequency for this preference.`	`Warning: 39.118MHz is the maximum frequency for this preference.`

`<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>`	`<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>`
`--------------`	`--------------`
`----------------------------------------------------------------------------`	`----------------------------------------------------------------------------`
`Preference \| Constraint\| Actual\|Levels`	`Preference \| Constraint\| Actual\|Levels`
`----------------------------------------------------------------------------`	`----------------------------------------------------------------------------`
`\| \| \|`	`\| \| \|`
`FREQUENCY NET "cpu_clkgen" 40.000000 \| \| \|`	`FREQUENCY NET "cpu_clkgen" 40.000000 \| \| \|`
`MHz ; \| 40.000 MHz\| 37.396 MHz\| 22 *`	`MHz ; \| 40.000 MHz\| 39.118 MHz\| 21 *`
`\| \| \|`	`\| \| \|`
`----------------------------------------------------------------------------`	`----------------------------------------------------------------------------`


`1 preference(marked by "*" above) not met.`	`1 preference(marked by "*" above) not met.`

`----------------------------------------------------------------------------`	`----------------------------------------------------------------------------`
`Critical Nets \| Loads\| Errors\| % of total`	`Critical Nets \| Loads\| Errors\| % of total`
`----------------------------------------------------------------------------`	`----------------------------------------------------------------------------`
`cpu0/alu/q8_out[7] \| 2\| 550\| 81.85%`	`cpu0/alu/alu16/N_2342 \| 1\| 178\| 89.90%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/N_160 \| 2\| 550\| 81.85%`	`cpu0/alu/q16_out[12] \| 2\| 178\| 89.90%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/N_2388 \| 1\| 550\| 81.85%`	`cpu0/alu/alu16/a16/q_out_2_cry_10 \| 1\| 178\| 89.90%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/arith_q[7] \| 2\| 550\| 81.85%`	`cpu0/alu/alu16/arith_q[12] \| 1\| 178\| 89.90%`
`\| \| \|`	`\| \| \|`
`cpu0/regs/left_1[7] \| 9\| 550\| 81.85%`	`cpu0/alu/alu16/a16/N_2375 \| 1\| 178\| 89.90%`
`\| \| \|`	`\| \| \|`
`cpu0/datamux_o_dest[7] \| 2\| 550\| 81.85%`	`cpu0/datamux_o_dest[12] \| 2\| 178\| 89.90%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/q_out_2_cry_6 \| 1\| 454\| 67.56%`	`cpu0/regs/left_1[12] \| 6\| 178\| 89.90%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/q_out_2_cry_4 \| 1\| 336\| 50.00%`	`cpu0/alu/alu16/a16/q_out_2_cry_8 \| 1\| 124\| 62.63%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/un8_q_out_cry_2 \| 1\| 334\| 49.70%`	`cpu0/alu/alu16/a16/un8_q_out_cry_4 \| 1\| 122\| 61.62%`
`\| \| \|`	`\| \| \|`
`cpu0/regs/SS_cry[7] \| 1\| 323\| 48.07%`	`cpu0/alu/alu16/a16/un8_q_out_cry_2 \| 1\| 106\| 53.54%`
`\| \| \|`	`\| \| \|`
`cpu0/regs/SU_cry[7] \| 1\| 323\| 48.07%`	`cpu0/alu/alu16/a16/un8_q_out_cry_6 \| 1\| 104\| 52.53%`
`\| \| \|`	`\| \| \|`
`cpu0/regs/N_250 \| 1\| 275\| 40.92%`	`cpu0/regs/SS_cry[13] \| 1\| 99\| 50.00%`
`\| \| \|`	`\| \| \|`
`cpu0/regs/N_286 \| 1\| 275\| 40.92%`	`cpu0/regs/SU_cry[13] \| 1\| 99\| 50.00%`
`\| \| \|`	`\| \| \|`
`cpu0/regs/SS_228_i1_mux \| 1\| 275\| 40.92%`	`cpu0/regs/N_255 \| 1\| 89\| 44.95%`
`\| \| \|`	`\| \| \|`
`cpu0/regs/SS_16[7] \| 1\| 275\| 40.92%`	`cpu0/regs/N_291 \| 1\| 89\| 44.95%`
`\| \| \|`	`\| \| \|`
`cpu0/regs/SU_212_i1_mux \| 1\| 275\| 40.92%`	`cpu0/regs/SS_235_i1_mux \| 1\| 89\| 44.95%`
`\| \| \|`	`\| \| \|`
`cpu0/regs/SU_16[7] \| 1\| 275\| 40.92%`	`cpu0/regs/SS_16[12] \| 1\| 89\| 44.95%`
`\| \| \|`	`\| \| \|`
`cpu0/regs/SS_cry[9] \| 1\| 267\| 39.73%`	`cpu0/regs/SU_219_i1_mux \| 1\| 89\| 44.95%`
`\| \| \|`	`\| \| \|`
`cpu0/regs/SU_cry[9] \| 1\| 267\| 39.73%`	`cpu0/regs/SU_16[12] \| 1\| 89\| 44.95%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/un8_q_out_cry_4 \| 1\| 252\| 37.50%`	`cpu0/alu/alu16/a16/q_out_2_cry_6 \| 1\| 78\| 39.39%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/un8_q_out_cry_0 \| 1\| 220\| 32.74%`	`cpu0/alu/alu16/a16/rb_in_i[0] \| 1\| 58\| 29.29%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/rb_in[0] \| 26\| 214\| 31.85%`	`cpu0/alu/alu16/a16/un8_q_out_cry_0 \| 1\| 58\| 29.29%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/rb_in_i[0] \| 1\| 208\| 30.95%`	`cpu0/alu/rb_in[0] \| 24\| 58\| 29.29%`
`\| \| \|`	`\| \| \|`
`cpu0/regs/SS_cry[11] \| 1\| 203\| 30.21%`	`cpu0/regs/SS_s[15] \| 1\| 55\| 27.78%`
`\| \| \|`	`\| \| \|`
`cpu0/regs/SU_cry[11] \| 1\| 203\| 30.21%`	`cpu0/regs/SU_s[15] \| 1\| 55\| 27.78%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/rb_in_i[1] \| 1\| 146\| 21.73%`	`cpu0/alu/alu16/a16/un8_q_out_cry_8 \| 1\| 54\| 27.27%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/rb_in[1] \| 26\| 146\| 21.73%`	`cpu0/alu/alu16/a16/q_out_2_cry_4 \| 1\| 46\| 23.23%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/q_out_2_cry_2 \| 1\| 144\| 21.43%`	`cpu0/regs/SS_s[14] \| 1\| 44\| 22.22%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/q_out_2_cry_3_0_RNO \| 1\| 114\| 16.96%`	`cpu0/regs/SU_s[14] \| 1\| 44\| 22.22%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/un8_q_out[3] \| 1\| 114\| 16.96%`	`cpu0/alu/alu16/a16/rb_in_i[1] \| 1\| 34\| 17.17%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/rb_in_i[2] \| 1\| 112\| 16.67%`	`cpu0/alu/rb_in[1] \| 24\| 34\| 17.17%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/rb_in[2] \| 23\| 112\| 16.67%`	`cpu0/alu/alu16/a16/rb_in_i[2] \| 1\| 32\| 16.16%`
`\| \| \|`	`\| \| \|`
`cpu0/regs/SS_cry[13] \| 1\| 112\| 16.67%`	`cpu0/alu/rb_in[2] \| 21\| 32\| 16.16%`
`\| \| \|`	`\| \| \|`
`cpu0/regs/SU_cry[13] \| 1\| 112\| 16.67%`	`cpu0/alu/alu16/a16/q_out_2_cry_9_0_RNO \| 1\| 30\| 15.15%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/q_out_2_cry_5_0_RNO_0 \| 1\| 108\| 16.07%`	`cpu0/alu/alu16/a16/un8_q_out[9] \| 1\| 30\| 15.15%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/un8_q_out[6] \| 1\| 108\| 16.07%`	`cpu0/alu/alu16/a16/q_out_2_cry_7_0_RNO \| 1\| 28\| 14.14%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/q_out_2_cry_3_0_RNO_0 \| 1\| 106\| 15.77%`	`cpu0/alu/alu16/a16/un8_q_out[7] \| 1\| 28\| 14.14%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/un8_q_out[4] \| 1\| 106\| 15.77%`	`cpu0/alu/alu16/a16/rb_in_i[4] \| 1\| 24\| 12.12%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/q_out_2_cry_5_0_RNO \| 1\| 104\| 15.48%`	`cpu0/alu/alu16/a16/rb_in_i[3] \| 1\| 24\| 12.12%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/un8_q_out[5] \| 1\| 104\| 15.48%`	`cpu0/alu/alu16/a16/q_out_2_cry_9_0_RNO_0\| 1\| 24\| 12.12%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/un8_q_out_cry_6 \| 1\| 96\| 14.29%`	`cpu0/alu/alu16/a16/un8_q_out[10] \| 1\| 24\| 12.12%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/q_out_2_cry_7_0_RNO \| 1\| 96\| 14.29%`	`cpu0/alu/alu16/a16/q_out_2_cry_7_0_RNO_0\| 1\| 24\| 12.12%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/un8_q_out[7] \| 1\| 96\| 14.29%`	`cpu0/alu/alu16/a16/un8_q_out[8] \| 1\| 24\| 12.12%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/rb_in_i[3] \| 1\| 82\| 12.20%`	`cpu0/alu/rb_in[4] \| 21\| 24\| 12.12%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/rb_in[3] \| 24\| 82\| 12.20%`	`cpu0/alu/rb_in[3] \| 22\| 24\| 12.12%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/q_out_2_cry_1_0_RNO_0 \| 1\| 74\| 11.01%`	`cpu0/alu/alu16/a16/q_out_2_cry_5_0_RNO \| 1\| 22\| 11.11%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/un8_q_out[2] \| 1\| 74\| 11.01%`	`cpu0/alu/alu16/a16/un8_q_out[5] \| 1\| 22\| 11.11%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/q_out_2_cry_1_0_RNO \| 1\| 70\| 10.42%`	`cpu0/alu/alu16/a16/q_out_2_cry_5_0_RNO_0\| 1\| 20\| 10.10%`
`\| \| \|`	`\| \| \|`
`cpu0/alu/alu8/a8/un8_q_out[1] \| 1\| 70\| 10.42%`	`cpu0/alu/alu16/a16/un8_q_out[6] \| 1\| 20\| 10.10%`
	`\| \| \|`
	`cpu0/alu/alu16/a16/q_out_2_cry_3_0_RNO \| 1\| 20\| 10.10%`
	`\| \| \|`
	`cpu0/alu/alu16/a16/un8_q_out[3] \| 1\| 20\| 10.10%`
`\| \| \|`	`\| \| \|`
`----------------------------------------------------------------------------`	`----------------------------------------------------------------------------`


`<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>`	`<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>`
`------------------------`	`------------------------`

`Found 1 clocks:`	`Found 1 clocks:`

`Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 290`	`Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 367`
`Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;`	`Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;`


`<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>`	`<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>`
`---------------`	`---------------`

`Timing errors: 672 Score: 491074`	`Timing errors: 198 Score: 60114`
`Cumulative negative slack: 491074`	`Cumulative negative slack: 60114`

`Constraints cover 1007472 paths, 1 nets, and 9180 connections (96.2% coverage)`	`Constraints cover 1107881 paths, 1 nets, and 9190 connections (95.5% coverage)`

`--------------------------------------------------------------------------------`	`--------------------------------------------------------------------------------`
`<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101</big></U></B>`	`<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101</big></U></B>`
`Mon Jan 6 06:54:33 2014`	`Thu Feb 6 15:35:22 2014`

`Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.`	`Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.`
`Copyright (c) 1995 AT&T Corp. All rights reserved.`	`Copyright (c) 1995 AT&T Corp. All rights reserved.`
`Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.`	`Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.`
`Copyright (c) 2001 Agere Systems All rights reserved.`	`Copyright (c) 2001 Agere Systems All rights reserved.`
Line 294...	Line 296...
`<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;`	`<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;`
`4096 items scored, 0 timing errors detected.`	`4096 items scored, 0 timing errors detected.`
`--------------------------------------------------------------------------------`	`--------------------------------------------------------------------------------`


`Passed: The following path meets requirements by 0.443ns`	`Passed: The following path meets requirements by 0.386ns`

`Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)`	`Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)`

`Source: FF Q cpu_clk (from cpu_clkgen +)`	`Source: FF Q reset_cnt[0] (from cpu_clkgen +)`
`Destination: FF Data in cpu_clk (to cpu_clkgen +)`	`Destination: FF Data in reset_cnt[0] (to cpu_clkgen +)`

`Delay: 0.430ns (53.5% logic, 46.5% route), 2 logic levels.`	`Delay: 0.330ns (39.7% logic, 60.3% route), 1 logic levels.`

`Constraint Details:`	`Constraint Details:`

`0.430ns physical path delay SLICE_383 to SLICE_383 meets`	`0.330ns physical path delay SLICE_444 to SLICE_444 meets`
`-0.013ns DIN_HLD and`	`-0.056ns LSR_HLD and`
`0.000ns delay constraint requirement (totaling -0.013ns) by 0.443ns`	`0.000ns delay constraint requirement (totaling -0.056ns) by 0.386ns`

`Physical Path Details:`	`Physical Path Details:`

`Data path SLICE_383 to SLICE_383:`	`Data path SLICE_444 to SLICE_444:`

`Name Fanout Delay (ns) Site Resource`	`Name Fanout Delay (ns) Site Resource`
`REG_DEL --- 0.131 SLICE_383.CLK to SLICE_383.Q0 SLICE_383 (from cpu_clkgen)`	`REG_DEL --- 0.131 SLICE_444.CLK to SLICE_444.Q0 SLICE_444 (from cpu_clkgen)`
`ROUTE 101 e 0.199 SLICE_383.Q0 to SLICE_383.A0 cpu_clk`	`ROUTE 5 e 0.199 SLICE_444.Q0 to SLICE_444.LSR reset_cnt[0] (to cpu_clkgen)`
`CTOF_DEL --- 0.099 SLICE_383.A0 to SLICE_383.F0 SLICE_383`
`ROUTE 1 e 0.001 SLICE_383.F0 to SLICE_383.DI0 cpu_clk_i (to cpu_clkgen)`
`--------`	`--------`
`0.430 (53.5% logic, 46.5% route), 2 logic levels.`	`0.330 (39.7% logic, 60.3% route), 1 logic levels.`

`<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>`	`<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>`
`--------------`	`--------------`
`----------------------------------------------------------------------------`	`----------------------------------------------------------------------------`
`Preference(MIN Delays) \| Constraint\| Actual\|Levels`	`Preference(MIN Delays) \| Constraint\| Actual\|Levels`
`----------------------------------------------------------------------------`	`----------------------------------------------------------------------------`
`\| \| \|`	`\| \| \|`
`FREQUENCY NET "cpu_clkgen" 40.000000 \| \| \|`	`FREQUENCY NET "cpu_clkgen" 40.000000 \| \| \|`
`MHz ; \| -\| -\| 2`	`MHz ; \| -\| -\| 1`
`\| \| \|`	`\| \| \|`
`----------------------------------------------------------------------------`	`----------------------------------------------------------------------------`


`All preferences were met.`	`All preferences were met.`
Line 341...	Line 341...
`<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>`	`<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>`
`------------------------`	`------------------------`

`Found 1 clocks:`	`Found 1 clocks:`

`Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 290`	`Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 367`
`Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;`	`Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;`


`<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>`	`<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>`
`---------------`	`---------------`

`Timing errors: 0 Score: 0`	`Timing errors: 0 Score: 0`
`Cumulative negative slack: 0`	`Cumulative negative slack: 0`

`Constraints cover 1007472 paths, 1 nets, and 9435 connections (98.9% coverage)`	`Constraints cover 1107881 paths, 1 nets, and 9531 connections (99.1% coverage)`



`<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>`	`<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>`
`---------------`	`---------------`

`Timing errors: 672 (setup), 0 (hold)`	`Timing errors: 198 (setup), 0 (hold)`
`Score: 491074 (setup), 0 (hold)`	`Score: 60114 (setup), 0 (hold)`
`Cumulative negative slack: 491074 (491074+0)`	`Cumulative negative slack: 60114 (60114+0)`
`--------------------------------------------------------------------------------`	`--------------------------------------------------------------------------------`

`--------------------------------------------------------------------------------`	`--------------------------------------------------------------------------------`

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[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809_tw1.html] - Diff between revs 9 and 10