Subversion Repositories 6809_6309_compatible_core

Date:        Mon Jan  6 06:54:11 2014

Date:        Thu Feb  6 15:34:32 2014

Run Time:00h:00m:03s

Run Time:00h:00m:06s

Run Time:00h:00m:01s

Run Time:00h:00m:02s

Run Time:00h:00m:14s

Run Time:00h:00m:31s

#Mon Jan  6 06:54:11 2014

#Thu Feb  6 15:34:32 2014

@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":699:23:699:27|Specified digits overflow the number's size

@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":732:23:732:27|Specified digits overflow the number's size

File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v changed - recompiling

File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v changed - recompiling

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":157:7:157:12|Synthesizing module shift8

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":158:7:158:12|Synthesizing module shift8

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":197:7:197:10|Synthesizing module alu8

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":198:7:198:10|Synthesizing module alu8

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":319:0:319:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":320:0:320:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":240:12:240:13|No assignment to n8

@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":241:12:241:13|No assignment to n8

@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":240:20:240:21|No assignment to z8

@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":241:20:241:21|No assignment to z8

@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":301:0:301:5|Pruning register regq8[7:0]

@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":302:0:302:5|Pruning register regq8[7:0]

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":603:7:603:12|Synthesizing module mul8x8

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":604:7:604:12|Synthesizing module mul8x8

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":128:7:128:13|Synthesizing module arith16

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":129:7:129:13|Synthesizing module arith16

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":325:7:325:11|Synthesizing module alu16

@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":326:7:326:11|Synthesizing module alu16

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":411:23:411:29|No assignment to wire arith_h

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":412:23:412:29|No assignment to wire arith_h

@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":517:0:517:5|Pruning register regq16[15:0]

@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":518:0:518:5|Pruning register regq16[15:0]

@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":418:6:418:13|Ignoring system task $display

@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":450:6:450:13|Ignoring system task $display

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1039:0:1039:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1074:0:1074:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":64:11:64:23|No assignment to wire alu8_o_result

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":67:11:67:23|No assignment to wire alu8_o_result

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":65:11:65:20|No assignment to wire alu8_o_CCR

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":68:11:68:20|No assignment to wire alu8_o_CCR

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit k_mem_dest[0] is always 1, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit k_mem_dest[1] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit k_mem_dest[1] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit next_mem_state[1] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit next_mem_state[1] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit next_mem_state[2] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register bit next_mem_state[2] is always 0, optimizing ...

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bits 2 to 1 of next_mem_state[5:0]

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Pruning register bits 2 to 1 of next_mem_state[5:0]

@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":31:14:31:21|No assignment to clk_div2

@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:14:37:21|No assignment to clk_div2

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|No assignment to wire cpu1_addr_o

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":42:25:42:35|No assignment to wire cpu1_addr_o

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:40:37:51|No assignment to wire cpu1_data_in

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:40:43:51|No assignment to wire cpu1_data_in

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|No assignment to wire cpu1_data_out

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:54:43:66|No assignment to wire cpu1_data_out

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:23:38:29|No assignment to wire cpu1_we

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":44:23:44:29|No assignment to wire cpu1_we

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:32:38:38|No assignment to wire cpu1_oe

@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":44:32:44:38|No assignment to wire cpu1_oe

@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.

@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:54:43:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.

@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.

@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":42:25:42:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.

@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":105:25:105:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.

@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":146:25:146:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Pruning register bits 5 to 3 of next_push_state[5:0]

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bits 5 to 3 of next_push_state[5:0]

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":329:18:329:20|Input port bits 7 to 4 of CCR[7:0] are unused

@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":330:18:330:20|Input port bits 7 to 4 of CCR[7:0] are unused

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Pruning register bits 15 to 13 of pipe0[15:0]

@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Pruning register bits 15 to 13 of pipe0[15:0]

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Register bit pipe0[12] is always 0, optimizing ...

@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Register bit pipe0[12] is always 0, optimizing ...

@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":613:0:613:5|Pruning register bit 12 of pipe0[12:0]

@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Pruning register bit 12 of pipe0[12:0]

@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":198:12:198:17|Input clk_in is unused

@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":199:12:199:17|Input clk_in is unused

@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":159:18:159:21|Input b_in is unused

@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":160:18:160:21|Input b_in is unused

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process took 0h:00m:04s realtime, 0h:00m:02s cputime

# Mon Jan  6 06:54:13 2014

# Thu Feb  6 15:34:36 2014

@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 83 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.

@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 95 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.

# Mon Jan  6 06:54:14 2014

# Thu Feb  6 15:34:40 2014

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs

Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 161MB)

Finished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 157MB peak: 159MB)

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs

Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 152MB peak: 163MB)

Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 152MB peak: 160MB)

@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":883:11:883:29|Pipelining module un75

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 160MB)

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":288:0:288:5|Register k_pp_regs[7:0] pushed in.

@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":143:35:143:85|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_2[16:0] from cpu0.alu.alu16.a16.un28_q_out[16:0]

@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":222:2:222:5|Pipelining module ea_reg_post_o[15:0]

@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":100:35:100:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.a8.q_out_2[8:0] from cpu0.alu.alu8.a8.un26_q_out[8:0]

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register IY[15:0] pushed in.

@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":140:35:140:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_1_0[16:0] from cpu0.alu.alu16.a16.un17_q_out[16:0]

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register IX[15:0] pushed in.

@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":99:35:99:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.a8.q_out_1_0[8:0] from cpu0.alu.alu8.a8.un17_q_out[8:0]

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_ind_ea[7:0] pushed in.

@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":254:2:254:5|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.ea.k_new_pc_4[15:0] from cpu0.un1_regs_o_pc[15:0]

@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register DP[7:0] pushed in.

Starting Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 152MB peak: 165MB)

Starting Early Timing Optimization (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 160MB)

Finished Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 152MB peak: 165MB)

Finished Early Timing Optimization (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 160MB)

Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 151MB peak: 165MB)

Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:09s; Memory used current: 151MB peak: 160MB)

Finished preparing to map (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 151MB peak: 165MB)

Finished preparing to map (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:11s; Memory used current: 151MB peak: 160MB)

Finished technology mapping (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 212MB peak: 229MB)

Finished technology mapping (Real Time elapsed 0h:00m:24s; CPU Time elapsed 0h:00m:13s; Memory used current: 202MB peak: 230MB)

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 167MB peak: 229MB)

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:14s; Memory used current: 166MB peak: 230MB)

Finished restoring hierarchy (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 169MB peak: 229MB)

Finished restoring hierarchy (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:15s; Memory used current: 168MB peak: 230MB)

1 non-gated/non-generated clock tree(s) driving 455 clock pin(s) of sequential element(s)

1 non-gated/non-generated clock tree(s) driving 596 clock pin(s) of sequential element(s)

342 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks

264 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks

@K:CKID0001       clk40_i             port                   455        cpu_clk

@K:CKID0001       clk40_i             port                   596        div

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 172MB peak: 229MB)

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:28s; CPU Time elapsed 0h:00m:16s; Memory used current: 170MB peak: 230MB)

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 176MB peak: 229MB)

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:17s; Memory used current: 174MB peak: 230MB)

# Timing Report written on Mon Jan  6 06:54:29 2014

# Timing Report written on Thu Feb  6 15:35:10 2014

Worst slack in design: 978.474

Worst slack in design: 978.937

CC3_top|clk40_i     1.0 MHz       46.5 MHz      1000.000      21.526        978.474     inferred     Inferred_clkgroup_0

CC3_top|clk40_i     1.0 MHz       47.5 MHz      1000.000      21.063        978.937     inferred     Inferred_clkgroup_0

CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    978.474  |  No paths    -      |  No paths    -      |  No paths    -

CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    978.937  |  No paths    -      |  No paths    -      |  No paths    -

cpu0.alu.rb_in[0]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[0]     1.302       978.474

cpu0.alu.rb_in[0]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[0]     1.296       978.937

cpu0.alu.rb_in[1]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[1]     1.302       978.617

cpu0.alu.rb_in[1]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[1]     1.296       979.080

cpu0.alu.rb_in[2]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[2]     1.292       978.627

cpu0.alu.rb_in[2]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[2]     1.284       979.092

cpu0.alu.rb_in[3]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[3]     1.296       978.766

cpu0.alu.rb_in[3]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[3]     1.288       979.231

cpu0.alu.rb_in[4]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[4]     1.292       978.770

cpu0.alu.rb_in[4]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[4]     1.284       979.235

cpu0.alu.ra_in[0]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[0]     1.305       979.039

cpu0.alu.ra_in[0]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[0]     1.299       979.502

cpu0.alu.ra_in[1]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[1]     1.309       979.178

cpu0.alu.rb_in[5]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[5]     1.284       979.533

cpu0.alu.ra_in[2]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[2]     1.309       979.178

cpu0.alu.rb_in[6]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[6]     1.272       979.545

cpu0.alu.ra_in[3]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[3]     1.305       979.324

cpu0.alu.ra_in[1]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[1]     1.299       979.645

cpu0.alu.ra_in[4]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[4]     1.292       979.338

cpu0.alu.ra_in[2]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[2]     1.299       979.645

cpu0.regs.SS[14]     CC3_top|clk40_i     FD1P3AX     D       SS_s[14]     999.894      978.474

cpu0.regs.SS[14]     CC3_top|clk40_i     FD1P3AX     D       SS_s[14]     999.894      978.937

cpu0.regs.SS[15]     CC3_top|clk40_i     FD1P3AX     D       SS_s[15]     999.894      978.474

cpu0.regs.SS[15]     CC3_top|clk40_i     FD1P3AX     D       SS_s[15]     999.894      978.937

cpu0.regs.SU[14]     CC3_top|clk40_i     FD1P3AX     D       SU_s[14]     999.894      978.474

cpu0.regs.SU[14]     CC3_top|clk40_i     FD1P3AX     D       SU_s[14]     999.894      978.937

cpu0.regs.SU[15]     CC3_top|clk40_i     FD1P3AX     D       SU_s[15]     999.894      978.474

cpu0.regs.SU[15]     CC3_top|clk40_i     FD1P3AX     D       SU_s[15]     999.894      978.937

cpu0.regs.SS[12]     CC3_top|clk40_i     FD1P3AX     D       SS_s[12]     999.894      978.617

cpu0.regs.SS[12]     CC3_top|clk40_i     FD1P3AX     D       SS_s[12]     999.894      979.080

cpu0.regs.SS[13]     CC3_top|clk40_i     FD1P3AX     D       SS_s[13]     999.894      978.617

cpu0.regs.SS[13]     CC3_top|clk40_i     FD1P3AX     D       SS_s[13]     999.894      979.080

cpu0.regs.SU[12]     CC3_top|clk40_i     FD1P3AX     D       SU_s[12]     999.894      978.617

cpu0.regs.SU[12]     CC3_top|clk40_i     FD1P3AX     D       SU_s[12]     999.894      979.080

cpu0.regs.SU[13]     CC3_top|clk40_i     FD1P3AX     D       SU_s[13]     999.894      978.617

cpu0.regs.SU[13]     CC3_top|clk40_i     FD1P3AX     D       SU_s[13]     999.894      979.080

cpu0.regs.SS[10]     CC3_top|clk40_i     FD1P3AX     D       SS_s[10]     999.894      978.760

cpu0.regs.SS[10]     CC3_top|clk40_i     FD1P3AX     D       SS_s[10]     999.894      979.223

cpu0.regs.SS[11]     CC3_top|clk40_i     FD1P3AX     D       SS_s[11]     999.894      978.760

cpu0.regs.SS[11]     CC3_top|clk40_i     FD1P3AX     D       SS_s[11]     999.894      979.223

    - Propagation time:                      21.420

    - Propagation time:                      20.957

    = Slack (critical) :                     978.474

    = Slack (critical) :                     978.937

    Number of logic level(s):                23

    Number of logic level(s):                22

---------------------------------------------------------------------------------------------------------

-----------------------------------------------------------------------------------------------------------

cpu0.alu.rb_in[0]                          FD1P3AX      Q        Out     1.302     1.302       -

cpu0.alu.rb_in[0]                            FD1P3AX      Q        Out     1.296     1.296       -

rb_in[0]                                   Net          -        -       -         -           26

rb_in[0]                                     Net          -        -       -         -           24

cpu0.alu.alu8.a8.un8_q_out_cry_0_0_RNO     INV          A        In      0.000     1.302       -

cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO     INV          A        In      0.000     1.296       -

cpu0.alu.alu8.a8.un8_q_out_cry_0_0_RNO     INV          Z        Out     0.568     1.870       -

cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO     INV          Z        Out     0.568     1.864       -

cpu0.alu.alu8.a8.un8_q_out_cry_0_0         CCU2D        A1       In      0.000     1.870       -

cpu0.alu.alu16.a16.un8_q_out_cry_0_0         CCU2D        A1       In      0.000     1.864       -

cpu0.alu.alu8.a8.un8_q_out_cry_0_0         CCU2D        COUT     Out     1.544     3.415       -

cpu0.alu.alu16.a16.un8_q_out_cry_0_0         CCU2D        COUT     Out     1.544     3.408       -

cpu0.alu.alu8.a8.un8_q_out_cry_1_0         CCU2D        CIN      In      0.000     3.415       -

cpu0.alu.alu16.a16.un8_q_out_cry_1_0         CCU2D        CIN      In      0.000     3.408       -

cpu0.alu.alu8.a8.un8_q_out_cry_1_0         CCU2D        S1       Out     1.549     4.964       -

cpu0.alu.alu16.a16.un8_q_out_cry_1_0         CCU2D        S1       Out     1.549     4.957       -

cpu0.alu.alu8.a8.q_out_2_cry_1_0_RNO_0     ORCALUT4     A        In      0.000     4.964       -

cpu0.alu.alu16.a16.q_out_2_cry_1_0_RNO_0     ORCALUT4     A        In      0.000     4.957       -

cpu0.alu.alu8.a8.q_out_2_cry_1_0_RNO_0     ORCALUT4     Z        Out     1.017     5.981       -

cpu0.alu.alu16.a16.q_out_2_cry_1_0_RNO_0     ORCALUT4     Z        Out     1.017     5.974       -

cpu0.alu.alu8.a8.q_out_2_cry_1_0           CCU2D        C1       In      0.000     5.981       -

cpu0.alu.alu16.a16.q_out_2_cry_1_0           CCU2D        C1       In      0.000     5.974       -

cpu0.alu.alu8.a8.q_out_2_cry_1_0           CCU2D        COUT     Out     1.544     7.525       -

cpu0.alu.alu16.a16.q_out_2_cry_1_0           CCU2D        COUT     Out     1.544     7.519       -

cpu0.alu.alu8.a8.q_out_2_cry_3_0           CCU2D        CIN      In      0.000     7.525       -

cpu0.alu.alu16.a16.q_out_2_cry_3_0           CCU2D        CIN      In      0.000     7.519       -

cpu0.alu.alu8.a8.q_out_2_cry_3_0           CCU2D        COUT     Out     0.143     7.668       -

cpu0.alu.alu16.a16.q_out_2_cry_3_0           CCU2D        COUT     Out     0.143     7.661       -

cpu0.alu.alu8.a8.q_out_2_cry_5_0           CCU2D        CIN      In      0.000     7.668       -

cpu0.alu.alu16.a16.q_out_2_cry_5_0           CCU2D        CIN      In      0.000     7.661       -

cpu0.alu.alu8.a8.q_out_2_cry_5_0           CCU2D        COUT     Out     0.143     7.811       -

cpu0.alu.alu16.a16.q_out_2_cry_5_0           CCU2D        COUT     Out     0.143     7.804       -

cpu0.alu.alu8.a8.q_out_2_cry_7_0           CCU2D        CIN      In      0.000     7.811       -

cpu0.alu.alu16.a16.q_out_2_cry_7_0           CCU2D        CIN      In      0.000     7.804       -

cpu0.alu.alu8.a8.q_out_2_cry_7_0           CCU2D        S0       Out     1.549     9.360       -

cpu0.alu.alu16.a16.q_out_2_cry_7_0           CCU2D        S0       Out     1.549     9.353       -

N_2388                                     Net          -        -       -         -           1

N_2370                                       Net          -        -       -         -           1

cpu0.alu.alu8.a8.q_out_3[7]                ORCALUT4     A        In      0.000     9.360       -

cpu0.alu.alu16.a16.q_out_3[7]                ORCALUT4     B        In      0.000     9.353       -

cpu0.alu.alu8.a8.q_out_3[7]                ORCALUT4     Z        Out     1.089     10.448      -

cpu0.alu.alu16.a16.q_out_3[7]                ORCALUT4     Z        Out     1.153     10.506      -

arith_q[7]                                 Net          -        -       -         -           2

arith_q[7]                                   Net          -        -       -         -           3

cpu0.alu.alu8.q_out_4_am[7]                ORCALUT4     A        In      0.000     10.448      -

cpu0.alu.alu16.q_out_1[7]                    ORCALUT4     A        In      0.000     10.506      -

cpu0.alu.alu8.q_out_4_am[7]                ORCALUT4     Z        Out     1.017     11.465      -

cpu0.alu.alu16.q_out_1[7]                    ORCALUT4     Z        Out     1.017     11.523      -

q_out_4_am[7]                              Net          -        -       -         -           1

N_60                                         Net          -        -       -         -           1

cpu0.alu.alu8.q_out_4[7]                   PFUMX        BLUT     In      0.000     11.465      -

cpu0.alu.alu16.q_out[7]                      PFUMX        ALUT     In      0.000     11.523      -

cpu0.alu.alu8.q_out_4[7]                   PFUMX        Z        Out     0.286     11.751      -

cpu0.alu.alu16.q_out[7]                      PFUMX        Z        Out     0.286     11.809      -

N_160                                      Net          -        -       -         -           2

q16_out[7]                                   Net          -        -       -         -           2

cpu0.alu.alu8.q_out_5_RNIRSTD1[7]          ORCALUT4     A        In      0.000     11.751      -

cpu0.alu.alu8.datamux_o_dest_bm[7]           ORCALUT4     B        In      0.000     11.809      -

cpu0.alu.alu8.q_out_5_RNIRSTD1[7]          ORCALUT4     Z        Out     1.089     12.840      -

cpu0.alu.alu8.datamux_o_dest_bm[7]           ORCALUT4     Z        Out     1.017     12.826      -

q8_out[7]                                  Net          -        -       -         -           2

datamux_o_dest_bm[7]                         Net          -        -       -         -           1

cpu0.alu.q_out[7]                          ORCALUT4     A        In      0.000     12.840      -

cpu0.alu.alu8.datamux_o_dest[7]              PFUMX        ALUT     In      0.000     12.826      -

cpu0.alu.q_out[7]                          ORCALUT4     Z        Out     0.449     13.289      -

cpu0.alu.alu8.datamux_o_dest[7]              PFUMX        Z        Out     0.286     13.112      -

cpu0.regs.path_left_data_RNIOEVA1[7]       ORCALUT4     B        In      0.000     13.575      -

cpu0.regs.left_1[7]                          ORCALUT4     A        In      0.000     13.112      -

cpu0.regs.path_left_data_RNIOEVA1[7]       ORCALUT4     Z        Out     1.273     14.848      -

cpu0.regs.left_1[7]                          ORCALUT4     Z        Out     1.273     14.385      -

cpu0.regs.SS_16_0[7]                       ORCALUT4     B        In      0.000     14.848      -

cpu0.regs.SS_16_0[7]                         ORCALUT4     B        In      0.000     14.385      -

cpu0.regs.SS_16_0[7]                       ORCALUT4     Z        Out     1.017     15.865      -

cpu0.regs.SS_16_0[7]                         ORCALUT4     Z        Out     1.017     15.402      -

cpu0.regs.SS_16[7]                         ORCALUT4     A        In      0.000     15.865      -

cpu0.regs.SS_16[7]                           ORCALUT4     A        In      0.000     15.402      -

cpu0.regs.SS_16[7]                         ORCALUT4     Z        Out     1.017     16.882      -

cpu0.regs.SS_16[7]                           ORCALUT4     Z        Out     1.017     16.418      -

cpu0.regs.SS_228_m3                        ORCALUT4     B        In      0.000     16.882      -

cpu0.regs.SS_230_m3                          ORCALUT4     B        In      0.000     16.418      -

cpu0.regs.SS_228_m3                        ORCALUT4     Z        Out     1.017     17.898      -

cpu0.regs.SS_230_m3                          ORCALUT4     Z        Out     1.017     17.435      -

SS_228_i1_mux                              Net          -        -       -         -           1

SS_230_i1_mux                                Net          -        -       -         -           1

cpu0.regs.SS_cry_0[6]                      CCU2D        C1       In      0.000     17.898      -

cpu0.regs.SS_cry_0[6]                        CCU2D        C1       In      0.000     17.435      -

cpu0.regs.SS_cry_0[6]                      CCU2D        COUT     Out     1.544     19.443      -

cpu0.regs.SS_cry_0[6]                        CCU2D        COUT     Out     1.544     18.980      -

cpu0.regs.SS_cry_0[8]                      CCU2D        CIN      In      0.000     19.443      -

cpu0.regs.SS_cry_0[8]                        CCU2D        CIN      In      0.000     18.980      -

cpu0.regs.SS_cry_0[8]                      CCU2D        COUT     Out     0.143     19.586      -

cpu0.regs.SS_cry_0[8]                        CCU2D        COUT     Out     0.143     19.122      -

cpu0.regs.SS_cry_0[10]                     CCU2D        CIN      In      0.000     19.586      -

cpu0.regs.SS_cry_0[10]                       CCU2D        CIN      In      0.000     19.122      -

cpu0.regs.SS_cry_0[10]                     CCU2D        COUT     Out     0.143     19.729      -

cpu0.regs.SS_cry_0[10]                       CCU2D        COUT     Out     0.143     19.265      -

cpu0.regs.SS_cry_0[12]                     CCU2D        CIN      In      0.000     19.729      -

cpu0.regs.SS_cry_0[12]                       CCU2D        CIN      In      0.000     19.265      -

cpu0.regs.SS_cry_0[12]                     CCU2D        COUT     Out     0.143     19.871      -

cpu0.regs.SS_cry_0[12]                       CCU2D        COUT     Out     0.143     19.408      -

cpu0.regs.SS_cry_0[14]                     CCU2D        CIN      In      0.000     19.871      -

cpu0.regs.SS_cry_0[14]                       CCU2D        CIN      In      0.000     19.408      -

cpu0.regs.SS_cry_0[14]                     CCU2D        S1       Out     1.549     21.420      -

cpu0.regs.SS_cry_0[14]                       CCU2D        S1       Out     1.549     20.957      -

cpu0.regs.SS[15]                           FD1P3AX      D        In      0.000     21.420      -

cpu0.regs.SS[15]                             FD1P3AX      D        In      0.000     20.957      -

=========================================================================================================

===========================================================================================================

Register bits: 439 of 6864 (6%)

Register bits: 580 of 6864 (8%)

I/O cells:       49

I/O cells:       69

CCU2D:          196

BB:             8

FD1P3AX:        393

FD1P3AX:        529

FD1S3AX:        28

FD1S3AX:        32

FD1S3IX:        2

FD1S3IX:        3

INV:            19

INV:            20

L6MUX21:        26

L6MUX21:        16

OB:             40

OB:             60

ORCALUT4:       2024

ORCALUT4:       2014

PFUMX:          222

PFUMX:          226

VHI:            13

VHI:            14

true:           8

true:           7

At Mapper Exit (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 44MB peak: 229MB)

At Mapper Exit (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:17s; Memory used current: 44MB peak: 230MB)

Process took 0h:00m:14s realtime, 0h:00m:14s cputime

Process took 0h:00m:30s realtime, 0h:00m:17s cputime

# Mon Jan  6 06:54:29 2014

# Thu Feb  6 15:35:11 2014

  On or above line 299 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 300 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 307 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 308 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 1762 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 1768 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 3985 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 3762 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 4141 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 3915 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 5267 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 4480 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 5492 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 4636 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 9169 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 8836 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 10988 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 10966 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 13438 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 13581 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 14340 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 14376 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 15057 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 15093 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 15354 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 16549 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 16157 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 17247 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 16308 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 18117 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 18673 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 18865 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 22261 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 22005 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 32987 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 32810 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 35566 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 35408 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 38271 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 38078 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 38689 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 38496 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 42846 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 43706 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 43639 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

  On or above line 44658 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_cry_0_0_S0_0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_cry_0_0_S1_0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_2_cry_15_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/un8_q_out_cry_15_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_2_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/un8_q_out_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un8_q_out_cry_7_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un9_q_out_cry_7_0_COUT' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un8_q_out_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un9_q_out_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un8_q_out_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un9_q_out_cry_0_0_S1' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_1_cry_0_0_S0' has no load

WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_1_cry_0_0_S0_0' has no load

WARNING - ngdbuild: DRC complete with 91 warnings

WARNING - ngdbuild: DRC complete with 86 warnings

   3019 blocks expanded

   3156 blocks expanded

   Number of registers:    439

   Number of registers:    580

      PFU registers:    429

      PFU registers:    570

   Number of SLICEs:          1218 out of  3432 (35%)

   Number of SLICEs:          1208 out of  3432 (35%)

      SLICEs(logic/ROM/RAM):   360 out of  2574 (14%)

      SLICEs(logic/ROM/RAM):   350 out of  2574 (14%)

          As Logic/ROM:    360 out of  2574 (14%)

          As Logic/ROM:    350 out of  2574 (14%)

   Number of logic LUT4s:     2043

   Number of logic LUT4s:     2034

   Number of ripple logic:    196 (392 LUT4s)

   Number of ripple logic:    186 (372 LUT4s)

   Total number of LUT4s:     2435

   Total number of LUT4s:     2406

   Number of PIO sites used: 49 + 4(JTAG) out of 115 (46%)

   Number of PIO sites used: 69 + 4(JTAG) out of 115 (63%)

     Net cpu_clkgen: 290 loads, 290 rising, 0 falling (Driver: PIO clk40_i )

     Net cpu_clkgen: 367 loads, 367 rising, 0 falling (Driver: PIO clk40_i )

   Number of Clock Enables:  36

   Number of Clock Enables:  37

     Net cpu_clk: 80 loads, 80 LSLICEs

     Net cpu0_we: 8 loads, 0 LSLICEs

     Net k_cpu_we_RNIKJPB: 8 loads, 0 LSLICEs

     Net textctrl/video_en_RNIFLVI: 8 loads, 0 LSLICEs

     Net textctrl/un1_CPU_OE_EN_0_a2: 8 loads, 0 LSLICEs

     Net textctrl/N_75_i: 4 loads, 4 LSLICEs

     Net textctrl/x_cnte: 4 loads, 4 LSLICEs

     Net textctrl/N_76_i: 4 loads, 4 LSLICEs

     Net textctrl/vsync_cnt_0_sqmuxa_4: 4 loads, 4 LSLICEs

     Net textctrl/tshift_1_sqmuxa: 4 loads, 4 LSLICEs

     Net un1_bios_en_0_a2: 4 loads, 0 LSLICEs

     Net textctrl/line_cnte: 2 loads, 2 LSLICEs

     Net cpu0/k_mul_cnt_RNI6QASC: 3 loads, 3 LSLICEs

     Net textctrl/vsync_cnt_0_sqmuxa: 4 loads, 4 LSLICEs

     Net cpu0/k_cpu_we_3_RNI4P5E: 8 loads, 8 LSLICEs

     Net cpu0/next_state_0_sqmuxa_4_RNIMOT3B: 3 loads, 3 LSLICEs

     Net cpu0/k_memhi_0_sqmuxa_RNIGVP52: 4 loads, 4 LSLICEs

     Net cpu0/G_9: 80 loads, 80 LSLICEs

     Net cpu0/mode53_0_RNIULGBO: 3 loads, 3 LSLICEs

     Net cpu0/k_ofshi_1_sqmuxa_RNIHOKL: 4 loads, 4 LSLICEs

     Net cpu0/k_eahi_0_sqmuxa_2_RNI9C57A: 4 loads, 4 LSLICEs

     Net cpu0/k_pp_regs60_RNI18KD3: 4 loads, 4 LSLICEs

     Net cpu0/un1_state_82_1_RNI3MDV1: 4 loads, 4 LSLICEs

     Net cpu0/state82_RNI5IM34: 4 loads, 4 LSLICEs

     Net cpu0/un1_state_100_i_o4_RNI60VG1: 4 loads, 4 LSLICEs

     Net cpu0/k_memhi_0_sqmuxa_RNIN4F02: 4 loads, 4 LSLICEs

     Net cpu0/k_pp_regs60_RNIHUUP8: 2 loads, 2 LSLICEs

     Net cpu0/un1_state_23_1_RNI2Q3P1: 4 loads, 4 LSLICEs

     Net cpu0/state_cnst_i_a15_1_0_RNI7NDU[5]: 4 loads, 4 LSLICEs

     Net cpu0/PC_1_sqmuxa_2_RNIK4633: 37 loads, 37 LSLICEs

     Net cpu0/k_new_pc29_0_o2_0_RNIRRPH4: 4 loads, 4 LSLICEs

     Net cpu0/k_new_pc28_RNILK8D5: 4 loads, 4 LSLICEs

     Net cpu0/k_new_pc29_0_o2_0_RNI939S3: 4 loads, 4 LSLICEs

     Net cpu0/regs/cff_1_sqmuxa_2_RNI1FDN: 18 loads, 18 LSLICEs

     Net cpu0/un1_state_50_1_i_o2_RNI0FLID: 4 loads, 4 LSLICEs

     Net cpu0/regs/eflag_0_sqmuxa_0_RNIOVLR: 4 loads, 4 LSLICEs

     Net cpu0/un1_state_21_RNIMEOJ: 4 loads, 4 LSLICEs

     Net cpu0/regs/IY_1_sqmuxa_2_1_0_RNIVEBV1: 25 loads, 25 LSLICEs

     Net cpu0/regs/cff_1_sqmuxa_2_RNI9H8F: 7 loads, 7 LSLICEs

     Net cpu0/regs/IX_0_sqmuxa_1_1_RNI2C2L3: 25 loads, 25 LSLICEs

     Net cpu0/regs/eflag_RNO: 1 loads, 1 LSLICEs

     Net cpu0/regs/DP_1_sqmuxa_1_1_0_RNIIANF1: 9 loads, 9 LSLICEs

     Net cpu0/regs/PC_1_sqmuxa_2_RNIDL992: 16 loads, 16 LSLICEs

     Net cpu0/regs/ACCB_0_sqmuxa_1_RNILJP21: 9 loads, 9 LSLICEs

     Net cpu0/regs/IY_1_sqmuxa_2_1_0_RNISJTR1: 8 loads, 8 LSLICEs

     Net cpu0/regs/ACCB22_RNIDCT43: 4 loads, 4 LSLICEs

     Net cpu0/regs/IX_0_sqmuxa_1_1_RNIVGKH3: 8 loads, 8 LSLICEs

     Net cpu0/un1_state_85_RNI07AH3: 2 loads, 2 LSLICEs

     Net cpu0/regs/DP_1_sqmuxa_1_1_0_RNIFF9C1: 5 loads, 5 LSLICEs

     Net cpu0/un1_state_18_2_RNINGR01: 4 loads, 4 LSLICEs

     Net cpu0/regs/ACCB_0_sqmuxa_1_RNIIOBV: 4 loads, 4 LSLICEs

     Net cpu0/un1_state_7_3_RNIREBA3: 8 loads, 8 LSLICEs

     Net cpu0/regs/un1_right_reg_4_RNIM2L32: 4 loads, 4 LSLICEs

     Net cpu0/state_3_sqmuxa_5_RNIE8SO9: 8 loads, 8 LSLICEs

     Net cpu0/un1_k_opcode_3_3_RNIC8F8I: 14 loads, 14 LSLICEs

     Net cpu0/un1_state_75_RNISTJ21: 2 loads, 2 LSLICEs

     Net cpu0/state57_RNI9L0F7[0]: 2 loads, 2 LSLICEs

     Net cpu0/un1_state_21_RNI6VAF: 4 loads, 4 LSLICEs

     Net cpu0/un1_state_73_RNI7H5S5: 2 loads, 2 LSLICEs

     Net cpu0/k_new_pc29_RNILU7S1: 4 loads, 4 LSLICEs

   Number of LSRs:  1

   Number of LSRs:  2

     Net cpu_clk: 101 loads

     Net cpu0/G_9: 93 loads

     Net cpu0/alu/rop_in[1]: 100 loads

     Net state_o_c[5]: 85 loads

     Net state_o_c[1]: 84 loads

     Net state_o_c[4]: 79 loads

     Net state_o_c[5]: 77 loads

     Net state_o_c[1]: 78 loads

     Net state_o_c[2]: 75 loads

     Net state_o_c[2]: 73 loads

     Net state_o_c[4]: 74 loads

     Net cpu0/alu/rop_in[1]: 72 loads

     Net cpu0/alu/rop_in[0]: 71 loads

     Net state_o_c[3]: 69 loads

     Net state_o_c[3]: 68 loads

     Net cpu0/alu/rop_in[0]: 67 loads

     Net cpu0/k_opcode[3]: 66 loads

     Net cpu0/k_opcode[3]: 59 loads

   Number of warnings:  11

   Number of warnings:  22

Total CPU Time: 0 secs

Total CPU Time: 1 secs

Total REAL Time: 0 secs

Total REAL Time: 5 secs

Peak Memory Usage: 195 MB

Peak Memory Usage: 196 MB

Mon Jan  6 06:54:33 2014

Thu Feb  6 15:35:22 2014

Timing errors: 672  Score: 491074

Timing errors: 198  Score: 60114

Cumulative negative slack: 491074

Cumulative negative slack: 60114

Constraints cover 1007472 paths, 1 nets, and 9180 connections (96.2% coverage)

Constraints cover 1107881 paths, 1 nets, and 9190 connections (95.5% coverage)

Mon Jan  6 06:54:33 2014

Thu Feb  6 15:35:22 2014

Constraints cover 1007472 paths, 1 nets, and 9435 connections (98.9% coverage)

Constraints cover 1107881 paths, 1 nets, and 9531 connections (99.1% coverage)

Timing errors: 672 (setup), 0 (hold)

Timing errors: 198 (setup), 0 (hold)

Score: 491074 (setup), 0 (hold)

Score: 60114 (setup), 0 (hold)

Cumulative negative slack: 491074 (491074+0)

Cumulative negative slack: 60114 (60114+0)

Total time: 0 secs

Total time: 3 secs

Mon Jan  6 06:54:33 2014

Thu Feb  6 15:35:23 2014

   PIO (prelim)   49+4(JTAG)/336     14% used

   PIO (prelim)   69+4(JTAG)/336     20% used

                  49+4(JTAG)/115     42% bonded

                  69+4(JTAG)/115     60% bonded

   SLICE           1218/3432         35% used

   SLICE           1208/3432         35% used

Number of Signals: 2816

Number of Signals: 2917

Number of Connections: 9541

Number of Connections: 9622