OpenCores
URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [bios2k.v] - Diff between revs 4 and 7

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 4 Rev 7
Line 1... Line 1...
/* Verilog netlist generated by SCUBA Diamond_2.2_Production (99) */
/* Verilog netlist generated by SCUBA Diamond_2.2_Production (99) */
/* Module Version: 7.2 */
/* Module Version: 7.2 */
/* /usr/local/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n bios2k -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type bram -wp 11 -rp 1010 -data_width 8 -rdata_width 8 -num_rows 2048 -cascade -1 -memfile test1.mem -memformat orca -writemodeA NORMAL -writemodeB NORMAL -e  */
/* /usr/local/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n bios2k -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type bram -wp 11 -rp 1010 -data_width 8 -rdata_width 8 -num_rows 2048 -cascade -1 -memfile test1.mem -memformat orca -writemodeA NORMAL -writemodeB NORMAL -e  */
/* Sat Dec 28 21:50:48 2013 */
/* Fri Jan  3 08:42:51 2014 */
 
 
 
 
`timescale 1 ns / 1 ps
`timescale 1 ns / 1 ps
module bios2k (DataInA, DataInB, AddressA, AddressB, ClockA, ClockB,
module bios2k (DataInA, DataInB, AddressA, AddressB, ClockA, ClockB,
    ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB, QA, QB)/* synthesis NGD_DRC_MASK=1 */;
    ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB, QA, QB)/* synthesis NGD_DRC_MASK=1 */;
Line 58... Line 58...
    defparam bios2k_0_0_1.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_0_1.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_0_1.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_0_1.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_0_1.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_0_1.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_0_1.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_0_1.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_0_1.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_0_1.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_0_1.INITVAL_00 = "0x0000000000000000000000000000000000000000000000000000000000000004002ECB0C07C1CC06" ;
    defparam bios2k_0_0_1.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000018010E01D0D8C90C01C0AE011880E" ;
    defparam bios2k_0_0_1.CSDECODE_B = "0b000" ;
    defparam bios2k_0_0_1.CSDECODE_B = "0b000" ;
    defparam bios2k_0_0_1.CSDECODE_A = "0b000" ;
    defparam bios2k_0_0_1.CSDECODE_A = "0b000" ;
    defparam bios2k_0_0_1.WRITEMODE_B = "NORMAL" ;
    defparam bios2k_0_0_1.WRITEMODE_B = "NORMAL" ;
    defparam bios2k_0_0_1.WRITEMODE_A = "NORMAL" ;
    defparam bios2k_0_0_1.WRITEMODE_A = "NORMAL" ;
    defparam bios2k_0_0_1.GSR = "ENABLED" ;
    defparam bios2k_0_0_1.GSR = "ENABLED" ;
Line 125... Line 125...
    defparam bios2k_0_1_0.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_1_0.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_1_0.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_1_0.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_1_0.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_1_0.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_1_0.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_1_0.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_1_0.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_1_0.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
    defparam bios2k_0_1_0.INITVAL_00 = "0x000000000000000000000000000000000000000000000000000000000000000F201A5F040941F008" ;
    defparam bios2k_0_1_0.INITVAL_00 = "0x0000000000000000000000000000000000000000000000000001C2F0508F04A4F042C51140418C08" ;
    defparam bios2k_0_1_0.CSDECODE_B = "0b000" ;
    defparam bios2k_0_1_0.CSDECODE_B = "0b000" ;
    defparam bios2k_0_1_0.CSDECODE_A = "0b000" ;
    defparam bios2k_0_1_0.CSDECODE_A = "0b000" ;
    defparam bios2k_0_1_0.WRITEMODE_B = "NORMAL" ;
    defparam bios2k_0_1_0.WRITEMODE_B = "NORMAL" ;
    defparam bios2k_0_1_0.WRITEMODE_A = "NORMAL" ;
    defparam bios2k_0_1_0.WRITEMODE_A = "NORMAL" ;
    defparam bios2k_0_1_0.GSR = "ENABLED" ;
    defparam bios2k_0_1_0.GSR = "ENABLED" ;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.