--===========================================================================--
|
--===========================================================================--
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-- --
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-- --
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-- Synthesizable PS/2 Keyboard Key map ROM --
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-- Synthesizable PS/2 Keyboard Key map ROM --
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-- --
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-- --
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--===========================================================================--
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--===========================================================================--
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--
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--
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-- File name : keymap_rom_slice.vhd
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-- File name : keymap_rom_slice.vhd
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--
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--
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-- Entity name : keymap_rom
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-- Entity name : keymap_rom
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--
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--
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-- Purpose : PS/2 key code look up table for PS/2 Keyboard
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-- Purpose : PS/2 key code look up table for PS/2 Keyboard
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-- Converts 7 bit key code to ASCII
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-- Converts 7 bit key code to ASCII
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-- Address bit 8 = Shift
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-- Address bit 8 = Shift
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-- Address bit 7 = CAPS Lock
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-- Address bit 7 = CAPS Lock
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-- Address bits 6 - 0 = Key code
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-- Address bits 6 - 0 = Key code
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-- Data bits 6 - 0 = ASCII code
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-- Data bits 6 - 0 = ASCII code
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-- Using constant array look up.
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-- Using constant array look up.
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--
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--
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-- Dependencies : ieee.std_logic_1164
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-- Dependencies : ieee.std_logic_1164
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-- ieee.std_logic_arith
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-- ieee.std_logic_arith
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_unsigned
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--
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--
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-- Uses : None
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-- Uses : None
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--
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--
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-- Author : John E. Kent
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-- Author : John E. Kent
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--
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--
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-- Email : dilbert57@opencores.org
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-- Email : dilbert57@opencores.org
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--
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--
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-- Web : http://opencores.org/project,system09
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-- Web : http://opencores.org/project,system09
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--
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--
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-- Copyright (C) 2004 - 2010 John Kent
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-- Copyright (C) 2004 - 2010 John Kent
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--
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--
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-- This program is free software: you can redistribute it and/or modify
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-- This program is free software: you can redistribute it and/or modify
|
-- it under the terms of the GNU General Public License as published by
|
-- it under the terms of the GNU General Public License as published by
|
-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
|
-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
|
-- You should have received a copy of the GNU General Public License
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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--===========================================================================--
|
--===========================================================================--
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-- --
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-- --
|
-- Revision History --
|
-- Revision History --
|
-- --
|
-- --
|
--===========================================================================--
|
--===========================================================================--
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--
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--
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-- Version Date Author Changes
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-- Version Date Author Changes
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--
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--
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-- 0.1 2004-10-18 John Kent Initial version
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-- 0.1 2004-10-18 John Kent Initial version
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--
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--
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-- 0.2 2007-01-28 John Kent Made entity compatible with block RAM versions
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-- 0.2 2007-01-28 John Kent Made entity compatible with block RAM versions
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--
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--
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-- 0.3 2007-02-03 John Kent Initialized with bit_vector
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-- 0.3 2007-02-03 John Kent Initialized with bit_vector
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--
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--
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-- 0.4 2010-06-17 John Kent Updated header and added GPL
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-- 0.4 2010-06-17 John Kent Updated header and added GPL
|
-- Renamed data_in and data_out signals
|
-- Renamed data_in and data_out signals
|
--
|
--
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--
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--
|
library IEEE;
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library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
|
|
|
entity keymap_rom is
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entity keymap_rom is
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Port (
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Port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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cs : in std_logic;
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rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (8 downto 0);
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addr : in std_logic_vector (8 downto 0);
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data_in : in std_logic_vector (7 downto 0);
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data_in : in std_logic_vector (7 downto 0);
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data_out : out std_logic_vector (7 downto 0)
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data_out : out std_logic_vector (7 downto 0)
|
);
|
);
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end keymap_rom;
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end keymap_rom;
|
|
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architecture rtl of keymap_rom is
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architecture rtl of keymap_rom is
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|
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type rom_array is array(0 to 15) of std_logic_vector (255 downto 0);
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type rom_array is array(0 to 15) of std_logic_vector (255 downto 0);
|
|
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constant rom_data : rom_array :=
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constant rom_data : rom_array :=
|
(
|
(
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x"00327761737a0000003171000000000000600900000000000000000000000000", -- 1F - 00
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x"00327761737a0000003171000000000000600900000000000000000000000000", -- 1F - 00
|
x"003837756a6d00000036796768626e0000357274667620000033346564786300", -- 3F - 20
|
x"003837756a6d00000036796768626e0000357274667620000033346564786300", -- 3F - 20
|
x"00005c005d0d000000003d5b00270000002d703b6c2f2e000039306f696b2c00", -- 5F - 40
|
x"00005c005d0d000000003d5b00270000002d703b6c2f2e000039306f696b2c00", -- 5F - 40
|
x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
|
x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
|
|
|
x"00325741535a00000031510000000000007e0900000000000000000000000000", -- 9F - 80
|
x"00325741535a00000031510000000000007e0900000000000000000000000000", -- 9F - 80
|
x"003837554a4d00000036594748424e0000355254465620000033344544584300", -- BF - A0
|
x"003837554a4d00000036594748424e0000355254465620000033344544584300", -- BF - A0
|
x"00005c005d0d000000003d5b00270000002d503b4c2f2e000039304f494b2c00", -- DF - C0
|
x"00005c005d0d000000003d5b00270000002d503b4c2f2e000039304f494b2c00", -- DF - C0
|
x"0000000000000000001b000000007f0000000000000000000008000000000000", -- FF - E0
|
x"0000000000000000001b000000007f0000000000000000000008000000000000", -- FF - E0
|
|
|
x"00405741535a00000021510000000000007e0900000000000000000000000000", -- 1F - 00
|
x"00405741535a00000021510000000000007e0900000000000000000000000000", -- 1F - 00
|
x"002a26554a4d0000005e594748424e0000255254465620000023244544584300", -- 3F - 20
|
x"002a26554a4d0000005e594748424e0000255254465620000023244544584300", -- 3F - 20
|
x"00007c007d0d000000002b7b00220000005f503a4c3f3e000028294f494b3c00", -- 5F - 40
|
x"00007c007d0d000000002b7b00220000005f503a4c3f3e000028294f494b3c00", -- 5F - 40
|
x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
|
x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
|
|
|
x"00407761737a0000002171000000000000600900000000000000000000000000", -- 9F - 80
|
x"00407761737a0000002171000000000000600900000000000000000000000000", -- 9F - 80
|
x"002a26756a6d0000005e796768626e0000257274667620000023246564786300", -- BF - A0
|
x"002a26756a6d0000005e796768626e0000257274667620000023246564786300", -- BF - A0
|
x"00007c007d0d000000002b7b00220000005f703a6c3f3e000028296f696b3c00", -- DF - C0
|
x"00007c007d0d000000002b7b00220000005f703a6c3f3e000028296f696b3c00", -- DF - C0
|
x"0000000000000000001b000000007f0000000000000000000008000000000000" -- FF - E0
|
x"0000000000000000001b000000007f0000000000000000000008000000000000" -- FF - E0
|
);
|
);
|
|
|
signal rom_out : std_logic_vector(255 downto 0);
|
signal rom_out : std_logic_vector(255 downto 0);
|
|
|
begin
|
begin
|
|
|
process( addr, rom_data, rom_out )
|
process( addr, rom_out )
|
begin
|
begin
|
rom_out <= rom_data(conv_integer(addr(8 downto 5)));
|
rom_out <= rom_data(conv_integer(addr(8 downto 5)));
|
data_out <= rom_out( conv_integer(addr(4 downto 0))*8+7 downto conv_integer(addr(4 downto 0))*8);
|
data_out <= rom_out( conv_integer(addr(4 downto 0))*8+7 downto conv_integer(addr(4 downto 0))*8);
|
end;
|
end process;
|
|
|
end architecture rtl;
|
end architecture rtl;
|
|
|
|
|
