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[/] [System09/] [trunk/] [rtl/] [System09_BurchED_B3/] [System09_BurchED_B3.vhd] - Diff between revs 66 and 107

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--===========================================================================----
--=============================================================================--
--
--                                                                             --
--  S Y N T H E Z I A B L E    System09 - SOC.
--  System09 - Synthesizable System On a Chip - VHDL FPGA core top level file. --
--
--                                                                             --
--  www.OpenCores.Org - September 2003
--=============================================================================--
--  This core adheres to the GNU public license  
--
--
-- File name      : System09_BurchED_B3.vhd
-- File name      : System09.vhd
--
--
-- Purpose        : This is the top level file for a 6809 instruction compatible system on a chip 
-- Purpose        : Top level file for 6809 compatible system on a chip
--                  It has been designed for the BurchED B3 Spartan2+ FPGA board
--                  Designed with Xilinx XC2S200 Spartan 2+ FPGA.
--                  using the Xilinx XC2S200 Spartan 2 FPGA and Xilinx ISE 7.1 software.
--                  Implemented With BurchED B3 FPGA board,
--                  It has been implemented with the BurchED B3 FPGA board, 
--                  B3-SRAM module and B3-FPGA-CPU-IO module
--                  modified B3-SRAM module and B3-FPGA-CPU-IO module. 
 
--                  It also supports an IDE CF card interface using a CF to IDE interface adapter.
 
--                  It uses a monochrome version of the VDU due to limitted Block RAM of XC2S200
--
--
-- Dependencies   : ieee.Std_Logic_1164
-- Dependencies   : ieee.Std_Logic_1164
--                  ieee.std_logic_unsigned
--                  ieee.std_logic_unsigned
--                  ieee.std_logic_arith
--                  ieee.std_logic_arith
--                  ieee.numeric_std
--                  ieee.numeric_std
--
--
-- Uses           : 
-- Uses           : 
--                  cpu09      (cpu09.vhd)      CPU core
--                  clk_div        (..\Spartan2\clk_div.vhd)       System Clock Divider
--                  mon_rom    (sys09bug_rom2k_b4.vhd) Monitor ROM
--                  cpu09          (..\VHDL\cpu09.vhd)             CPU core
--                  dat_ram    (datram.vhd)     Dynamic Address Translation
--                  B3_SRAM        (..\VHDL\B3_SRAM.vhd)           BurchED B3 SRAM module interface
--                  acia_6850  (ACIA_6850.vhd) ACIA / MiniUART
--                  acia6850       (..\VHDL\acia6850.vhd)          RS232 Serial Interface
--                             (ACIA_RX.vhd)
--                  ACIA_Clock     (..\VHDL\ACIA_Clock.vhd)        ACIA Baud Rate Clock Divider
--                             (ACIA_TX.vhd)
--                  keyboard       (..\VHDL\keyboard.vhd)          PS/2 Keyboard register interface
--                  ACIA_Clock (ACIA_Clock.vhd) ACIA Baud Clock Divider
--                  ps2_keyboard   (..\VHDL\ps2_keyboard.vhd)      PS/2 Keyboard interface logic
--                  keyboard   (keyboard.vhd)   PS/2 Keyboard Interface
--                  keymap_rom     (..\Spartan2\keymap_rom_b4.vhd) PS/2 Keyboard key code look up table
--                  vdu8       (vdu8.vhd)       80 x 25 Video Display
--                  vdu8_mono      (..\VHDL\vdu8_mono.vhd)         80 x 25 Monochrome Visual Display Unit.
--                  timer      (timer.vhd)      Timer module
--                  char_rom       (..\Spartan2\char_rom2k_b4.vhd) Character Generator ROM
--                  trap            (trap.vhd)       Bus Trap interrupt
--                  ram_2k         (..\Spartan2\ram2k_b4.vhd)      Text buffer RAM
--                  ioport     (ioport.vhd)     Parallel I/O port.
--                  timer          (..\VHDL\timer.vhd)             Timer module
 
--                  trap           (..\VHDL\trap.vhd)              Bus Trap interrupt
 
--                  spp            (..\VHDL\spp.vhd)               Simple Parallel Port
 
--                  peripheral_bus (..\VHDL\peripheral_bus.vhd)    16 bit IDE Peripheral Bus interface
 
--                  sys09bug_F800  (..\Spartan2\sys09b3s_b4.vhd)   Sysbug09 Monitor ROM
 
--                  dat_ram        (..\VHDL\datram.vhd)            Dynamic Address Translation (DAT)
-- 
-- 
-- Author         : John E. Kent      
-- Author         : John E. Kent      
--                  dilbert57@opencores.org
--                  dilbert57@opencores.org
 
--
-- Memory Map     :
-- Memory Map     :
--
--
 
-- $0000 - $DFFF System RAM (256K Mapped via DAT)
-- $E000 - ACIA (SWTPc)
-- $E000 - ACIA (SWTPc)
-- $E010 - Reserved for FD1771 FDC (SWTPc)
-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
-- $E020 - Keyboard
-- $E020 - Keyboard
-- $E030 - VDU
-- $E030 - VDU
-- $E040 - Compact Flash
-- $E040 - Reserved for SWTPc MP-T (was Compact Flash)
-- $E050 - Timer
-- $E050 - Timer
-- $E060 - Bus trap
-- $E060 - Bus Trap (Hardware Breakpoint Interrupt Logic)
-- $E070 - Parallel I/O
-- $E070 - Reserved for Trace Buffer
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
-- $E080 - Reserved for SWTPc MP-ID 6821 PIA (?)
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
-- $E090 - Reserved for SWTPc MP-ID 6840 PTM (?)
-- $E0A0
-- $E0A0 - SPP Printer Port
-- $E0B0
-- $E0B0 - Reserved
-- $E0C0 - Trace logic
-- $E0C0 - Reserved
 
-- $E100 - $E13F IDE / Compact Flash Card
 
-- $E140 - $E17F Reserved for Ethernet MAC (XESS)
 
-- $E180 - $E1BF Reserved for Expansion Slot 0 (XESS)
 
-- $E1C0 - $E1FF Reserved for Expansion Slot 1 (XESS)
 
-- $E200 - $EFFF Dual Port RAM interface
 
-- $F000 - $F7FF Reserved SWTPc DMAF-2
 
-- $F800 - $FFFF Sys09bug ROM (Read only)
 
-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
 
--
 
--
 
--  Copyright (C) 2003 - 2010 John Kent
 
--
 
--  This program is free software: you can redistribute it and/or modify
 
--  it under the terms of the GNU General Public License as published by
 
--  the Free Software Foundation, either version 3 of the License, or
 
--  (at your option) any later version.
 
--
 
--  This program is distributed in the hope that it will be useful,
 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 
--  GNU General Public License for more details.
 
--
 
--  You should have received a copy of the GNU General Public License
 
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
--
--===========================================================================----
--===========================================================================--
--
--
-- Revision History:
-- Revision History:
 
--
--===========================================================================--
--===========================================================================--
-- Version 0.1 - 20 March 2003
-- Version 0.1 - 20 March 2003
-- Version 0.2 - 30 March 2003
-- Version 0.2 - 30 March 2003
-- Version 0.3 - 29 April 2003
-- Version 0.3 - 29 April 2003
-- Version 0.4 - 29 June 2003
-- Version 0.4 - 29 June 2003
Line 87... Line 121...
-- the VDU divides 50 MHz to generate a 
-- the VDU divides 50 MHz to generate a 
-- 25 MHz VDU Pixel Clock and a 12.5 MHz CPU clock
-- 25 MHz VDU Pixel Clock and a 12.5 MHz CPU clock
-- Changed Monitor ROM signals to make it look like
-- Changed Monitor ROM signals to make it look like
-- a standard 2K memory block
-- a standard 2K memory block
-- Re-assigned I/O port assignments so it is possible to run KBUG9
-- Re-assigned I/O port assignments so it is possible to run KBUG9
-- $E000 - ACIA
 
-- $E010 - Keyboard
 
-- $E020 - VDU
 
-- $E030 - Compact Flash
 
-- $E040 - Timer
 
-- $E050 - Bus trap
 
-- $E060 - Parallel I/O
 
--
--
-- Version 1.5 - 3rd February 2007 - John Kent
-- Version 1.5 - 3rd February 2007 - John Kent
-- Changed VDU8 to use external clock divider
-- Changed VDU8 to use external clock divider
-- renamed miniUART to ACIA_6850
-- renamed miniUART to ACIA_6850
-- Memory decoding of ROM & IO now uses DAT
-- Memory decoding of ROM & IO now uses DAT
Line 114... Line 141...
-- Mapped in all 16 bits of the CF data bus.
-- Mapped in all 16 bits of the CF data bus.
--
--
-- Version 1.8 - 1st July 2007 - John Kent
-- Version 1.8 - 1st July 2007 - John Kent
-- Copied B5-X300 top level to B3 version.
-- Copied B5-X300 top level to B3 version.
-- 
-- 
 
-- Version 2.0 - 6th September 2008 - John Kent
 
-- added IDE interface for a CF card.
 
-- Used separate Clock DLL for generating clocks
 
--
 
-- Version 2.1 - 23rd Februaury 2008 - John Kent
 
-- Renamed Monitor ROM
 
--
 
-- Version 2.2 - 28th August 2010 - John Kent
 
-- Renamed ACIA_6850 to acia6850
 
-- Updated CPU & VDU component signal names & generics
 
-- Made peripheral bus interface a separate component
 
-- Made BED_SRAM a separate component
 
-- Made the LED flasher a separate component
 
-- Updated Header
 
--
--===========================================================================
--===========================================================================
--
--
library ieee;
library ieee;
   use ieee.std_logic_1164.all;
   use ieee.std_logic_1164.all;
   use IEEE.STD_LOGIC_ARITH.ALL;
   use IEEE.STD_LOGIC_ARITH.ALL;
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library unisim;
library unisim;
        use unisim.vcomponents.all;
        use unisim.vcomponents.all;
 
 
entity System09 is
entity System09 is
  port(
  port(
    SysClk      : in  Std_Logic;  -- System Clock input
    clk_in      : in  Std_Logic;  -- System Clock input
         Reset_n     : in  Std_logic;  -- Master Reset input (active low)
    rst_n       : in  Std_logic;  -- Master Reset input (active low)
    LED         : out std_logic;  -- Diagnostic LED Flasher
    LED         : out Std_logic;  -- Diagnostic LED Flasher
 
 
 
    -- B3-SRAM Memory Interface signals
 
 
    -- Memory Interface signals
 
    ram_csn     : out Std_Logic;
    ram_csn     : out Std_Logic;
    ram_wrln    : out Std_Logic;
    ram_wrln    : out Std_Logic;
    ram_wrun    : out Std_Logic;
    ram_wrun    : out Std_Logic;
    ram_addr    : out Std_Logic_Vector(16 downto 0);
    ram_addr    : out Std_Logic_Vector(16 downto 0);
    ram_data    : inout Std_Logic_Vector(15 downto 0);
    ram_data    : inout Std_Logic_Vector(15 downto 0);
 
 
         -- Stuff on the peripheral board
    -- End of B3-SRAM Memory Interface signals
 
 
 
    -- B3-FPGA-CPU-IO Module signals
 
 
 
    -- Asychronous Communications Interface Adapater signals (RS232 Serial Port) ($E00X)
 
    acia_rxd    : in  Std_Logic;
 
    acia_txd    : out Std_Logic;
 
    acia_rts_n  : out Std_Logic;
 
    acia_cts_n  : in  Std_Logic;
 
 
         -- PS/2 Keyboard
    -- PS/2 Keyboard Interface ($E02X)
         kb_clock    : inout Std_logic;
         kb_clock    : inout Std_logic;
         kb_data     : inout Std_Logic;
         kb_data     : inout Std_Logic;
 
 
         -- PS/2 Mouse interface
         -- PS/2 Mouse interface
--       mouse_clock : in  Std_Logic;
--       mouse_clock : in  Std_Logic;
--       mouse_data  : in  Std_Logic;
--       mouse_data  : in  Std_Logic;
 
 
         -- Uart Interface
    -- Visual Display Unit output signals ($E03X)
    rxbit       : in  Std_Logic;
    vga_vsync   : out Std_Logic;
         txbit       : out Std_Logic;
    vga_hsync   : out Std_Logic;
    rts_n       : out Std_Logic;
    vga_blue    : out std_logic_vector(1 downto 0);
    cts_n       : in  Std_Logic;
    vga_green   : out std_logic_vector(1 downto 0);
 
    vga_red     : out std_logic_vector(1 downto 0);
         -- CRTC output signals
 
         v_drive     : out Std_Logic;
    -- Buzzer
    h_drive     : out Std_Logic;
 
    blue_lo     : out std_logic;
 
    blue_hi     : out std_logic;
 
    green_lo    : out std_logic;
 
    green_hi    : out std_logic;
 
    red_lo      : out std_logic;
 
    red_hi      : out std_logic;
 
--         buzzer      : out std_logic;
--         buzzer      : out std_logic;
 
 
-- Compact Flash
    -- End of B3-FPGA-CPU-IO Module signals
--    cf_rst_n     : out std_logic;
 
--    cf_cs0_n     : out std_logic;
 
--    cf_cs1_n     : out std_logic;
 
--    cf_rd_n      : out std_logic;
 
--    cf_wr_n      : out std_logic;
 
--    cf_cs16_n    : out std_logic;
 
--    cf_a         : out std_logic_vector(2 downto 0);
 
--    cf_d         : inout std_logic_vector(15 downto 0);
 
--    cf_d         : inout std_logic_vector(7 downto 0);
 
 
 
-- Parallel I/O port
 
    porta        : inout std_logic_vector(7 downto 0);
 
    portb        : inout std_logic_vector(7 downto 0);
 
 
 
-- CPU bus
 
         bus_clk      : out std_logic;
 
         bus_reset    : out std_logic;
 
         bus_rw       : out std_logic;
 
         bus_csn      : out std_logic;
 
    bus_addr     : out std_logic_vector(19 downto 0);
 
         bus_data     : inout std_logic_vector(7 downto 0);
 
 
 
-- timer
    -- Parallel Printer Port    ($E0AX)
    timer_out    : out std_logic
    pp_data      : out std_logic_vector(7 downto 0);
 
    pp_stat      : in  std_logic_vector(7 downto 3);
 
    pp_ctrl      : out std_logic_vector(3 downto 0);
 
 
 
    -- Peripheral Bus ($E100 - $E1FF) 
 
    pb_iord_n    : out std_logic;
 
    pb_iowr_n    : out std_logic;
 
    pb_addr      : out std_logic_vector(2 downto 0);
 
    pb_data      : inout std_logic_vector(15 downto 0);
 
 
 
    -- IDE Compact Flash ($E100 - $E13F)
 
    ide_rst_n    : out std_logic; -- ide pin 1
 
    ide_cs0_n    : out std_logic; -- ide pin 37
 
    ide_cs1_n    : out std_logic; -- ide pin 38
 
    ide_dmarq    : in  std_logic; -- ide pin 21
 
    ide_dmack_n  : out std_logic; -- ide pin 29
 
    ide_iordy    : in  std_logic; -- ide pin 27
 
    ide_con_csel : out std_logic; -- ide pin 28
 
    ide_intrq    : in  std_logic; -- ide pin 31
 
    ide_iocs16_n : in  std_logic; -- ide pin 32
 
    ide_pdiag_n  : in  std_logic; -- ide pin 34
 
    ide_dasp_n   : out std_logic; -- ide pin 39
 
 
 
    -- Dual port RAM interface bus
 
    bus_clk      : in  std_logic;
 
    bus_cs_n     : in  std_logic;
 
    bus_rw       : in  std_logic;
 
    bus_addr     : in  std_logic_vector(12 downto 0);
 
    bus_data_in  : in  std_logic_vector(7 downto 0);
 
    bus_data_out : out std_logic_vector(7 downto 0)
         );
         );
end System09;
end System09;
 
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Architecture for System09
-- Architecture for System09
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture rtl of System09 is
architecture rtl of System09 is
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- constants
  -- constants
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  constant SYS_Clock_Frequency  : integer := 50000000;  -- FPGA System Clock
  constant SYS_CLK_FREQ  : integer := 50000000;  -- FPGA System Clock
  constant PIX_Clock_Frequency  : integer := 25000000;  -- VGA Pixel Clock
  constant VGA_CLK_FREQ  : integer := 25000000;  -- VGA Pixel Clock
  constant CPU_Clock_Frequency  : integer := 12500000;  -- CPU Clock
  constant CPU_CLK_FREQ  : integer := 12500000;  -- CPU Clock
  constant BAUD_Rate            : integer := 57600;       -- Baud Rate
  constant BAUD_RATE     : integer := 57600;      -- Baud Rate
  constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
  constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
 
 
  type hold_state_type is ( hold_release_state, hold_request_state );
 
 
 
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Signals
  -- Signals
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Monitor ROM
 
  signal rom_data_out  : Std_Logic_Vector(7 downto 0);
 
  signal rom_cs        : std_logic;
 
 
 
  -- UART Interface signals
 
  signal uart_data_out : Std_Logic_Vector(7 downto 0);
 
  signal uart_cs       : Std_Logic;
 
  signal uart_irq      : Std_Logic;
 
  signal uart_clk       : Std_Logic;
 
  signal DCD_n         : Std_Logic;
 
 
 
  -- timer
 
  signal timer_data_out : std_logic_vector(7 downto 0);
 
  signal timer_cs    : std_logic;
 
  signal timer_irq   : std_logic;
 
 
 
  -- trap
  -- System Clock
  signal trap_cs         : std_logic;
  signal sys_clk       : std_logic;
  signal trap_data_out   : std_logic_vector(7 downto 0);
 
  signal trap_irq        : std_logic;
 
 
 
 
 
  -- trace
 
--  signal trace_cs          : std_logic;
 
--  signal trace_data_out    : std_logic_vector(7 downto 0);
 
--  signal trace_irq         : std_logic;
 
--  signal bank_cs           : std_logic;
 
--  signal bank_data_out     : std_logic_vector(7 downto 0);
 
 
 
  -- Parallel I/O port
 
  signal ioport_data_out : std_logic_vector(7 downto 0);
 
  signal ioport_cs    : std_logic;
 
 
 
  -- compact flash port
 
--  signal cf_data_out : std_logic_vector(7 downto 0);
 
--  signal cf_cs       : std_logic;
 
--  signal cf_rd       : std_logic;
 
--  signal cf_wr       : std_logic;
 
--  signal cf_hold     : std_logic;
 
--  signal cf_release  : std_logic;
 
--  signal cf_count    : std_logic_vector(3 downto 0);
 
--  signal cf_hold_state : hold_state_type;
 
 
 
  -- keyboard port
 
  signal keyboard_data_out : std_logic_vector(7 downto 0);
 
  signal keyboard_cs       : std_logic;
 
  signal keyboard_irq      : std_logic;
 
 
 
  -- RAM
 
  signal ram_cs      : std_logic; -- memory chip select
 
  signal ram_wrl     : std_logic; -- memory write lower
 
  signal ram_wru     : std_logic; -- memory write upper
 
  signal ram_data_out    : std_logic_vector(7 downto 0);
 
 
 
  -- CPU Interface signals
  -- CPU Interface signals
  signal cpu_reset    : Std_Logic;
  signal cpu_rst       : Std_Logic;
  signal cpu_clk      : Std_Logic;
  signal cpu_clk      : Std_Logic;
  signal cpu_rw       : std_logic;
  signal cpu_rw       : std_logic;
  signal cpu_vma      : std_logic;
  signal cpu_vma      : std_logic;
  signal cpu_halt     : std_logic;
  signal cpu_halt     : std_logic;
  signal cpu_hold     : std_logic;
  signal cpu_hold     : std_logic;
Line 278... Line 278...
  signal cpu_nmi      : std_logic;
  signal cpu_nmi      : std_logic;
  signal cpu_addr     : std_logic_vector(15 downto 0);
  signal cpu_addr     : std_logic_vector(15 downto 0);
  signal cpu_data_in  : std_logic_vector(7 downto 0);
  signal cpu_data_in  : std_logic_vector(7 downto 0);
  signal cpu_data_out : std_logic_vector(7 downto 0);
  signal cpu_data_out : std_logic_vector(7 downto 0);
 
 
  -- Dynamic address translation
  -- B3 Static RAM            ($0000 - $DFFF)
  signal dat_cs       : std_logic;
  signal ram_cs        : std_logic; -- memory chip select
  signal dat_addr     : std_logic_vector(7 downto 0);
  signal ram_data_out  : std_logic_vector(7 downto 0);
 
 
 
  -- ACIA Console serial port ($E000 - $E00F)
 
  signal acia_data_out : Std_Logic_Vector(7 downto 0);
 
  signal acia_cs       : Std_Logic;
 
  signal acia_irq      : Std_Logic;
 
  signal acia_clk      : Std_Logic;
 
 
 
  -- PS/2 Keyboard interface  ($E02X)
 
  signal kbd_data_out  : std_logic_vector(7 downto 0);
 
  signal kbd_cs        : std_logic;
 
  signal kbd_irq       : std_logic;
 
 
  -- Video Display Unit
  -- Visual Display Unit      ($E03X)
  signal pix_clk      : std_logic;
  signal vga_clk       : std_logic;
  signal vdu_cs       : std_logic;
  signal vdu_cs       : std_logic;
  signal vdu_data_out : std_logic_vector(7 downto 0);
  signal vdu_data_out : std_logic_vector(7 downto 0);
  signal vga_red      : std_logic;
  signal vga_red_o     : std_logic;
  signal vga_green    : std_logic;
  signal vga_green_o   : std_logic;
  signal vga_blue     : std_logic;
  signal vga_blue_o    : std_logic;
 
 
 
  -- Timer                    ($E05X)
 
  signal timer_data_out : std_logic_vector(7 downto 0);
 
  signal timer_cs      : std_logic;
 
  signal timer_irq     : std_logic;
 
 
  -- external bus I/O
  -- Bus trap                 ($E06X)
 
  signal trap_cs       : std_logic;
 
  signal trap_data_out : std_logic_vector(7 downto 0);
 
  signal trap_irq      : std_logic;
 
 
 
  -- Trace                    ($E07X)
 
--  signal trace_cs       : std_logic;
 
--  signal trace_data_out : std_logic_vector(7 downto 0);
 
--  signal trace_irq      : std_logic;
 
 
 
  -- Simple Parallel I/O port ($E0AX)
 
  signal spp_data_out  : std_logic_vector(7 downto 0);
 
  signal spp_cs        : std_logic;
 
 
 
  -- Peripheral Bus           ($E1XX)
 
  signal pb_cs         : std_logic;
 
  signal pb_data_out   : std_logic_vector(7 downto 0);
 
  signal pb_hold       : std_logic;
 
 
 
  -- Peripheral Bus Chip Selects ($E1XX)
 
  signal ide_cs        : std_logic;      -- IDE CF interface   ($E100 - $E13F)
 
  signal ether_cs      : std_logic;  -- Ethernet interface ($E140 - $E17F)      
 
  signal slot1_cs      : std_logic;      -- Expansion slot1    ($E180 - $E1BF)
 
  signal slot2_cs      : std_logic;      -- Expansion slot 2   ($E1C0 - $E1FF)
 
 
 
  -- Dual Port RAM for Bus Interfacing  ($E200 - $E7FF)
 
  signal dpr_data_out  : std_logic_vector(7 downto 0);
 
  signal dpr_cs        : std_logic;
 
  signal dpr_wr        : std_logic;
 
 
 
  -- External Bus Interface
 
  signal bus_iclk     : std_logic;
 
  signal bus_gclk     : std_logic;
  signal bus_cs       : std_logic;
  signal bus_cs       : std_logic;
 
  signal bus_wr       : std_logic;
 
 
 
  -- Monitor ROM ($F800 - $FFFF)
 
  signal rom_data_out  : Std_Logic_Vector(7 downto 0);
 
  signal rom_cs        : std_logic;
 
 
 
  -- Dynamic Address Translation        ($FFF0 - $FFFF)
 
  signal dat_cs       : std_logic;
 
  signal dat_addr     : std_logic_vector(7 downto 0);
 
 
 
-----------------------------------------------------------------
 
--
 
--                     Clock generator
 
--
 
-----------------------------------------------------------------
 
 
 
component clock_div
 
  port(
 
    clk_in      : in  std_Logic;  -- System Clock input
 
         sys_clk     : out std_logic;  -- System Clock Out    (1/1)
 
         vga_clk     : out std_logic;  -- VGA Pixel Clock Out (1/2)
 
    cpu_clk     : out std_logic   -- CPU Clock Out       (1/4)
 
  );
 
end component;
 
 
 
-----------------------------------------------------------------
 
--
 
--                      LED Flasher
 
--
 
-----------------------------------------------------------------
 
 
 
component flasher
 
  port (
 
    clk      : in  std_logic;           -- Clock input
 
    rst      : in  std_logic;           -- Reset input (active high)
 
    LED      : out Std_Logic            -- LED output        
 
  );
 
end component;
 
 
  -- Flashing Led test signals
 
  signal countL       : std_logic_vector(23 downto 0);
 
  signal clock_div    : std_logic_vector(1 downto 0);
 
 
 
-----------------------------------------------------------------
-----------------------------------------------------------------
--
--
-- CPU09 CPU core
--                  6809 Compatible CPU core
--
--
-----------------------------------------------------------------
-----------------------------------------------------------------
 
 
component cpu09
component cpu09
  port (
  port (
         clk:        in std_logic;
         clk:        in std_logic;
    rst:      in        std_logic;
    rst:      in        std_logic;
    rw:      out        std_logic;              -- Asynchronous memory interface
    rw        : out std_logic;
    vma:             out        std_logic;
    vma:             out        std_logic;
    address:  out       std_logic_vector(15 downto 0);
    addr      : out std_logic_vector(15 downto 0);
    data_in:  in        std_logic_vector(7 downto 0);
    data_in:  in        std_logic_vector(7 downto 0);
         data_out: out std_logic_vector(7 downto 0);
         data_out: out std_logic_vector(7 downto 0);
         halt:     in  std_logic;
         halt:     in  std_logic;
         hold:     in  std_logic;
         hold:     in  std_logic;
         irq:      in  std_logic;
         irq:      in  std_logic;
         nmi:      in  std_logic;
         nmi:      in  std_logic;
         firq:     in  std_logic
         firq:     in  std_logic
  );
  );
end component;
end component;
 
 
 
-----------------------------------------------------------------
----------------------------------------
 
--
--
-- SBUG Block RAM Monitor ROM
-- Dynamic Address Translation Registers ($FFF0 - $FFFF)
--
--
----------------------------------------
-----------------------------------------------------------------
component mon_rom
component dat_ram
    port (
    port (
       clk   : in  std_logic;
       clk   : in  std_logic;
       rst   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
    addr_lo  : in  std_logic_vector(3 downto 0);
       wdata : in  std_logic_vector (7 downto 0);
    addr_hi  : in  std_logic_vector(3 downto 0);
       rdata : out std_logic_vector (7 downto 0)
    data_in  : in  std_logic_vector(7 downto 0);
 
    data_out : out std_logic_vector(7 downto 0)
    );
    );
end component;
end component;
 
 
 
-------------------------------------------------
----------------------------------------
 
--
--
-- Dynamic Address Translation Registers
-- Sys09Bug Block RAM Monitor ROM ($F800-$FFFF)
--
--
----------------------------------------
-------------------------------------------------
component dat_ram
component sys09bug_F800
  port (
  port (
    clk:      in  std_logic;
    clk:      in  std_logic;
         rst:      in  std_logic;
         rst:      in  std_logic;
         cs:       in  std_logic;
         cs:       in  std_logic;
 
     addr     : in  std_logic_vector (10 downto 0);
         rw:       in  std_logic;
         rw:       in  std_logic;
         addr_lo:  in  std_logic_vector(3 downto 0);
 
         addr_hi:  in  std_logic_vector(3 downto 0);
 
    data_in:  in  std_logic_vector(7 downto 0);
    data_in:  in  std_logic_vector(7 downto 0);
         data_out: out std_logic_vector(7 downto 0)
         data_out: out std_logic_vector(7 downto 0)
         );
         );
end component;
end component;
 
 
-----------------------------------------------------------------
-----------------------------------------------------------------
--
--
-- 6850 ACIA/UART
-- 6850 ACIA RS232 Interface  ($E000 - $E00F)
--
--
-----------------------------------------------------------------
-----------------------------------------------------------------
 
 
component ACIA_6850
component acia6850
  port (
  port (
     clk      : in  Std_Logic;  -- System Clock
     clk      : in  Std_Logic;  -- System Clock
     rst      : in  Std_Logic;  -- Reset input (active high)
     rst      : in  Std_Logic;  -- Reset input (active high)
     cs       : in  Std_Logic;  -- miniUART Chip Select
     cs       : in  Std_Logic;  -- miniUART Chip Select
     rw       : in  Std_Logic;  -- Read / Not Write
     rw       : in  Std_Logic;  -- Read / Not Write
     irq      : out Std_Logic;  -- Interrupt
     irq      : out Std_Logic;  -- Interrupt
     Addr     : in  Std_Logic;  -- Register Select
     addr     : in  Std_Logic;  -- Register Select
     DataIn   : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
     data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
     DataOut  : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
     data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
     RxC      : in  Std_Logic;  -- Receive Baud Clock
     RxC      : in  Std_Logic;  -- Receive Baud Clock
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
     RxD      : in  Std_Logic;  -- Receive Data
     RxD      : in  Std_Logic;  -- Receive Data
     TxD      : out Std_Logic;  -- Transmit Data
     TxD      : out Std_Logic;  -- Transmit Data
          DCD_n    : in  Std_Logic;  -- Data Carrier Detect
          DCD_n    : in  Std_Logic;  -- Data Carrier Detect
Line 390... Line 471...
--
--
-----------------------------------------------------------------
-----------------------------------------------------------------
 
 
component ACIA_Clock
component ACIA_Clock
  generic (
  generic (
     SYS_Clock_Frequency  : integer :=  SYS_Clock_Frequency;
     SYS_CLK_FREQ  : integer := SYS_CLK_FREQ;
          ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
     ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
  );
  );
  port (
  port (
     clk      : in  Std_Logic;  -- System Clock Input
     clk      : in  Std_Logic;  -- System Clock Input
          ACIA_clk : out Std_logic   -- ACIA Clock output
     acia_clk : out Std_logic   -- ACIA Clock output
  );
  );
end component;
end component;
 
 
----------------------------------------
----------------------------------------
--
--
-- Timer module
-- PS/2 Keyboard ($E020 - $E02F)
--
--
----------------------------------------
----------------------------------------
 
 
component timer
component keyboard
 
  generic(
 
     KBD_CLK_FREQ : integer := CPU_CLK_FREQ
 
  );
  port (
  port (
     clk       : in std_logic;
     clk       : in std_logic;
     rst       : in std_logic;
     rst       : in std_logic;
     cs        : in std_logic;
     cs        : in std_logic;
     rw        : in std_logic;
     rw        : in std_logic;
     addr      : in std_logic;
     addr      : in std_logic;
     data_in   : in std_logic_vector(7 downto 0);
     data_in   : in std_logic_vector(7 downto 0);
          data_out  : out std_logic_vector(7 downto 0);
          data_out  : out std_logic_vector(7 downto 0);
          irq       : out std_logic;
          irq       : out std_logic;
     timer_in  : in std_logic;
     kbd_clk     : inout std_logic;
          timer_out : out std_logic
     kbd_data    : inout std_logic
 
  );
 
end component;
 
 
 
----------------------------------------
 
--
 
-- Video Display Unit. ($E030 - $E03F)
 
--
 
----------------------------------------
 
component vdu8_mono
 
  generic(
 
    VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
 
         VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
 
         VGA_HOR_CHAR_PIXELS    : integer := 8;  -- PIXELS 0.32us
 
         VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us
 
         VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us
 
         VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us
 
         VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
 
         VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
 
         VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
 
         VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
 
         VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
 
  );
 
  port(
 
    -- control register interface
 
    vdu_clk      : in  std_logic;        -- CPU Clock - 12.5MHz
 
    vdu_rst      : in  std_logic;
 
    vdu_cs       : in  std_logic;
 
    vdu_addr     : in  std_logic_vector(2 downto 0);
 
    vdu_rw       : in  std_logic;
 
    vdu_data_in  : in  std_logic_vector(7 downto 0);
 
    vdu_data_out : out std_logic_vector(7 downto 0);
 
 
 
    -- vga port connections
 
    vga_clk      : in  std_logic;       -- VGA Pixel Clock - 25 MHz
 
    vga_red_o    : out std_logic;
 
    vga_green_o  : out std_logic;
 
    vga_blue_o   : out std_logic;
 
    vga_hsync_o  : out std_logic;
 
    vga_vsync_o  : out std_logic
 
  );
 
end component;
 
 
 
----------------------------------------
 
--
 
-- Timer module  ($E050 - $E05F)
 
--
 
----------------------------------------
 
 
 
component timer
 
  port (
 
    clk       : in std_logic;
 
    rst       : in std_logic;
 
    cs        : in std_logic;
 
    addr      : in std_logic;
 
    rw        : in std_logic;
 
    data_in   : in std_logic_vector(7 downto 0);
 
    data_out  : out std_logic_vector(7 downto 0);
 
    irq       : out std_logic
          );
          );
end component;
end component;
 
 
------------------------------------------------------------
------------------------------------------------------------
--
--
-- Bus Trap logic
-- Bus Trap / Hardware Breakpoint ($E060 - $E06F)
--
--
------------------------------------------------------------
------------------------------------------------------------
 
 
component trap
component trap
        port (
        port (
Line 442... Line 584...
  );
  );
end component;
end component;
 
 
------------------------------------------------------------
------------------------------------------------------------
--
--
-- Bus Trace logic
-- Bus Trace logic      ($E070 - $E07F)
--
--
------------------------------------------------------------
------------------------------------------------------------
--component trace is
--component trace is
--  port (      
--  port (      
--    clk           : in  std_logic;
--    clk           : in  std_logic;
Line 464... Line 606...
--  );
--  );
--end component;
--end component;
 
 
----------------------------------------
----------------------------------------
--
--
-- Dual 8 bit Parallel I/O module
-- Simple Parallel Port ($E0A0 - $E0AF)
--
--
----------------------------------------
----------------------------------------
component ioport
component spp
        port (
        port (
         clk       : in  std_logic;
         clk       : in  std_logic;
    rst       : in  std_logic;
    rst       : in  std_logic;
    cs        : in  std_logic;
    cs        : in  std_logic;
 
    addr      : in  std_logic_vector(2 downto 0);
    rw        : in  std_logic;
    rw        : in  std_logic;
    addr      : in  std_logic_vector(1 downto 0);
 
    data_in   : in  std_logic_vector(7 downto 0);
    data_in   : in  std_logic_vector(7 downto 0);
         data_out  : out std_logic_vector(7 downto 0);
         data_out  : out std_logic_vector(7 downto 0);
         porta_io  : inout std_logic_vector(7 downto 0);
    irq       : out std_logic;
         portb_io  : inout std_logic_vector(7 downto 0)
    hold      : out std_logic;
 
    spp_data  : out std_logic_vector(7 downto 0);
 
    spp_stat  : in  std_logic_vector(7 downto 3);
 
    spp_ctrl  : out std_logic_vector(3 downto 0)
         );
         );
end component;
end component;
 
 
----------------------------------------
------------------------------------------------------------
--
--
-- PS/2 Keyboard
-- Peripheral Bus interface (IDE CF) ($E100 - $E1FF)
--
--
----------------------------------------
------------------------------------------------------------
 
 
component keyboard
component peripheral_bus is
  generic(
 
  KBD_Clock_Frequency : integer := CPU_Clock_Frequency
 
  );
 
  port(
  port(
  clk             : in    std_logic;
    --
  rst             : in    std_logic;
    -- CPU Interface signals
  cs              : in    std_logic;
    --
  rw              : in    std_logic;
    clk      : in  std_logic;                     -- System Clock
  addr            : in    std_logic;
    rst      : in  std_logic;                     -- Reset input (active high)
  data_in         : in    std_logic_vector(7 downto 0);
    cs       : in  std_logic;                     -- Peripheral Bus Chip Select
  data_out        : out   std_logic_vector(7 downto 0);
    addr     : in  std_logic_vector(7 downto 0);  -- Register Select
  irq             : out   std_logic;
    rw       : in  std_logic;                     -- Read / Not Write
  kbd_clk         : inout std_logic;
    data_in  : in  std_logic_vector(7 downto 0);  -- Data Bus In 
  kbd_data        : inout std_logic
    data_out : out std_logic_vector(7 downto 0);  -- Data Bus Out
 
    hold     : out std_logic;                     -- Hold bus cycle output
 
    --
 
    -- Peripheral Bus Interface Signals
 
    -- IO + ($00 - $FF) 
 
    -- (for compatibility with XSA-3S1000 / XST 3.0)
 
    --
 
    pb_rd_n  : out   std_logic; -- ide pin 25
 
    pb_wr_n  : out   std_logic; -- ide pin 23
 
    pb_addr  : out   std_logic_vector( 4 downto 0);
 
    pb_data  : inout std_logic_vector(15 downto 0);
 
 
 
    -- Peripheral chip selects on Peripheral Bus 
 
    ide_cs   : out  std_logic;  -- IDE / CF interface ($00 - $3F)
 
    eth_cs   : out  std_logic;  -- Ethernet interface ($40 - $7F)
 
    sl1_cs   : out  std_logic;  -- Expansion slot 1   ($80 - $BF)
 
    sl2_cs   : out  std_logic   -- Expansion slot 2   ($C0 - $FF)
  );
  );
end component;
end component;
 
 
----------------------------------------
------------------------------------------------------------
--
--
-- Video Display Unit.
-- External Bus interface Dual port RAM ($E200 - $EFFF)
--
--
----------------------------------------
------------------------------------------------------------
component vdu8_mono
 
      generic(
 
        VDU_CLOCK_FREQUENCY    : integer := CPU_Clock_Frequency; -- HZ
 
        VGA_CLOCK_FREQUENCY    : integer := PIX_Clock_Frequency; -- HZ
 
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
 
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS
 
             VGA_PIXELS_PER_CHAR    : integer := 8;  -- PIXELS
 
             VGA_LINES_PER_CHAR     : integer := 16; -- LINES
 
             VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
 
             VGA_HOR_SYNC           : integer := 96; -- PIXELS
 
             VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
 
             VGA_VER_BACK_PORCH     : integer := 13; -- LINES
 
             VGA_VER_SYNC           : integer := 1;  -- LINES
 
             VGA_VER_FRONT_PORCH    : integer := 36  -- LINES
 
      );
 
      port(
 
                -- control register interface
 
      vdu_clk      : in  std_logic;      -- CPU Clock - 12.5MHz
 
      vdu_rst      : in  std_logic;
 
                vdu_cs       : in  std_logic;
 
                vdu_rw       : in  std_logic;
 
                vdu_addr     : in  std_logic_vector(2 downto 0);
 
      vdu_data_in  : in  std_logic_vector(7 downto 0);
 
      vdu_data_out : out std_logic_vector(7 downto 0);
 
 
 
      -- vga port connections
component RAMB4_S8_S8
                vga_clk      : in  std_logic;   -- VGA Pixel Clock - 25 MHz
port (
      vga_red_o    : out std_logic;
  RSTA:  IN  std_logic;
      vga_green_o  : out std_logic;
  CLKA:  IN  std_logic;
      vga_blue_o   : out std_logic;
  ENA:   IN  std_logic;
      vga_hsync_o  : out std_logic;
  WEA:   IN  std_logic;
      vga_vsync_o  : out std_logic
  ADDRA: IN  std_logic_vector(8 downto 0);
 
  DIA:   IN  std_logic_vector(7 downto 0);
 
  DOA:   OUT std_logic_vector(7 downto 0);
 
  RSTB:  IN  std_logic;
 
  CLKB:  IN  std_logic;
 
  ENB:   IN  std_logic;
 
  WEB:   IN  std_logic;
 
  ADDRB: IN  std_logic_vector(8 downto 0);
 
  DIB:   IN  std_logic_vector(7 downto 0);
 
  DOB:   OUT std_logic_vector(7 downto 0)
   );
   );
end component;
end component;
 
 
 
component IBUF
 
port (
 
  I : IN  std_logic;
 
  O : OUT std_logic
 
  );
 
end component;
 
 
component BUFG
component BUFG
  port (
  port (
                i: in  std_logic;
  I : IN  std_logic;
                o: out std_logic
  O : OUT std_logic
 
  );
 
end component;
 
 
 
------------------------------------------------------------
 
--
 
--           BED SRAM interface ($0000 - $DFFF)
 
--
 
------------------------------------------------------------
 
component BED_SRAM
 
  port (
 
    --
 
    -- CPU Interface signals
 
    --
 
    clk       : in  std_logic;                     -- System Clock (twice the CPU clock)
 
    rst       : in  std_logic;                     -- Reset input (active high)
 
    cs        : in  std_logic;                     -- RAM Chip Select
 
    addr      : in  std_logic_vector(17 downto 0); -- RAM address bus
 
    rw        : in  std_logic;                     -- Read / Not Write
 
    data_in   : in  std_logic_vector(7 downto 0);  -- Data Bus In 
 
    data_out  : out std_logic_vector(7 downto 0);  -- Data Bus Out
 
    --
 
    -- B3_SRAM Interface Signals
 
    --
 
    ram_csn   : out   Std_Logic;
 
    ram_wrln  : out   Std_Logic;
 
    ram_wrun  : out   Std_Logic;
 
    ram_addr  : out   Std_Logic_Vector(16 downto 0);
 
    ram_data  : inout Std_Logic_Vector(15 downto 0)
 
 
  );
  );
end component;
end component;
 
 
begin
begin
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Instantiation of internal components
  -- Instantiation of internal components
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
 
----------------------------------------
 
--
 
-- Clock generator
 
--
 
----------------------------------------
 
my_clock_div: clock_div port map (
 
    clk_in   => clk_in,   -- Clock input
 
    sys_clk  => sys_clk,  -- System Clock Out    (1/1)
 
    vga_clk  => vga_clk,  -- VGA Pixel Clock Out (1/2)
 
    cpu_clk  => cpu_clk   -- CPU Clock Out       (1/4)
 
  );
 
 
 
-----------------------------------------
 
--
 
-- LED Flasher
 
--
 
-----------------------------------------
 
 
 
my_LED_flasher : flasher port map (
 
    clk      => cpu_clk,
 
    rst      => cpu_rst,
 
    LED      => LED
 
  );
 
 
----------------------------------------
----------------------------------------
--
--
-- CPU09 CPU Core
-- CPU09 CPU Core
--
--
----------------------------------------
----------------------------------------
my_cpu : cpu09  port map (
my_cpu : cpu09  port map (
         clk         => cpu_clk,
         clk         => cpu_clk,
    rst       => cpu_reset,
    rst       => cpu_rst,
    rw       => cpu_rw,
    rw       => cpu_rw,
    vma       => cpu_vma,
    vma       => cpu_vma,
    address   => cpu_addr(15 downto 0),
    addr      => cpu_addr(15 downto 0),
    data_in   => cpu_data_in,
    data_in   => cpu_data_in,
         data_out  => cpu_data_out,
         data_out  => cpu_data_out,
         halt      => cpu_halt,
         halt      => cpu_halt,
         hold      => cpu_hold,
         hold      => cpu_hold,
         irq       => cpu_irq,
         irq       => cpu_irq,
Line 580... Line 781...
         firq      => cpu_firq
         firq      => cpu_firq
  );
  );
 
 
----------------------------------------
----------------------------------------
--
--
-- SBUG / KBUG / SYS09BUG Monitor ROM
-- Dynamic Address Translation ($FFF0-$FFFF)
--
--
----------------------------------------
----------------------------------------
my_rom : mon_rom port map (
my_dat : dat_ram port map (
       clk   => cpu_clk,
       clk   => cpu_clk,
                 rst   => cpu_reset,
    rst        => cpu_rst,
                 cs    => rom_cs,
    cs         => dat_cs,
                 rw    => '1',
    rw         => cpu_rw,
       addr  => cpu_addr(10 downto 0),
    addr_hi    => cpu_addr(15 downto 12),
                 wdata => cpu_data_out,
    addr_lo    => cpu_addr(3 downto 0),
       rdata => rom_data_out
    data_in    => cpu_data_out,
 
    data_out   => dat_addr(7 downto 0)
    );
    );
 
 
----------------------------------------
----------------------------------------
--
--
-- Dynamic Address Translation Registers
-- SYS09BUG Monitor ROM ($F800-$FFFF)
--
--
----------------------------------------
----------------------------------------
my_dat : dat_ram port map (
my_rom : SYS09BUG_F800 port map (
    clk        => cpu_clk,
    clk        => cpu_clk,
         rst        => cpu_reset,
       rst      => cpu_rst,
         cs         => dat_cs,
       cs       => rom_cs,
         rw         => cpu_rw,
       rw       => '1',
         addr_hi    => cpu_addr(15 downto 12),
       addr     => cpu_addr(10 downto 0),
         addr_lo    => cpu_addr(3 downto 0),
 
    data_in    => cpu_data_out,
    data_in    => cpu_data_out,
         data_out   => dat_addr(7 downto 0)
       data_out => rom_data_out
         );
         );
 
 
----------------------------------------
----------------------------------------
--
--
-- ACIA/UART Serial interface
-- ACIA RS232 Serial interface ($E000-$E00F)
--
--
----------------------------------------
----------------------------------------
my_ACIA  : ACIA_6850 port map (
my_ACIA  : acia6850 port map (
 
    --
 
    -- CPU Interface
 
    --
         clk         => cpu_clk,
         clk         => cpu_clk,
         rst       => cpu_reset,
    rst       => cpu_rst,
    cs        => uart_cs,
    cs        => acia_cs,
         rw        => cpu_rw,
         rw        => cpu_rw,
    irq       => uart_irq,
    irq       => acia_irq,
    Addr      => cpu_addr(0),
    addr      => cpu_addr(0),
         Datain    => cpu_data_out,
    data_in   => cpu_data_out,
         DataOut   => uart_data_out,
    data_out  => acia_data_out,
         RxC       => uart_clk,
    --
         TxC       => uart_clk,
    -- RS232 Interface
         RxD       => rxbit,
    --
         TxD       => txbit,
    RxC       => acia_clk,
         DCD_n     => dcd_n,
    TxC       => acia_clk,
         CTS_n     => cts_n,
    RxD       => acia_rxd,
         RTS_n     => rts_n
    TxD       => acia_txd,
 
    DCD_n     => '0',
 
    CTS_n     => acia_cts_n,
 
    RTS_n     => acia_rts_n
         );
         );
 
 
----------------------------------------
----------------------------------------
--
--
-- ACIA Clock
-- ACIA Baud Clock
--
--
----------------------------------------
----------------------------------------
my_ACIA_Clock : ACIA_Clock
my_ACIA_Clock : ACIA_Clock
  generic map(
  generic map(
    SYS_Clock_Frequency  => SYS_Clock_Frequency,
    SYS_CLK_FREQ  => SYS_CLK_FREQ,
         ACIA_Clock_Frequency => ACIA_Clock_Frequency
    ACIA_CLK_FREQ => ACIA_CLK_FREQ
  )
  )
  port map(
  port map(
    clk        => SysClk,
    clk        => sys_clk,
    acia_clk   => uart_clk
    acia_clk   => acia_clk
  );
  );
 
 
----------------------------------------
----------------------------------------
--
--
-- PS/2 Keyboard Interface
-- PS/2 Keyboard Interface ($E020-$E02F)
--
--
----------------------------------------
----------------------------------------
my_keyboard : keyboard
my_keyboard : keyboard
   generic map (
   generic map (
        KBD_Clock_Frequency => CPU_Clock_frequency
    KBD_CLK_FREQ => CPU_CLK_FREQ
        )
        )
   port map(
   port map(
        clk          => cpu_clk,
        clk          => cpu_clk,
        rst          => cpu_reset,
    rst          => cpu_rst,
        cs           => keyboard_cs,
    cs           => kbd_cs,
        rw           => cpu_rw,
        rw           => cpu_rw,
        addr         => cpu_addr(0),
        addr         => cpu_addr(0),
        data_in      => cpu_data_out(7 downto 0),
        data_in      => cpu_data_out(7 downto 0),
        data_out     => keyboard_data_out(7 downto 0),
    data_out     => kbd_data_out(7 downto 0),
        irq          => keyboard_irq,
    irq          => kbd_irq,
        kbd_clk      => kb_clock,
        kbd_clk      => kb_clock,
        kbd_data     => kb_data
        kbd_data     => kb_data
        );
        );
 
 
----------------------------------------
------------------------------------------------
--
--
-- Video Display Unit instantiation
-- Video Display Unit instantiation ($E030-$E03F)
--
--
----------------------------------------
-------------------------------------------------
my_vdu : vdu8_mono
my_vdu : vdu8_mono
  generic map(
  generic map(
      VDU_CLOCK_FREQUENCY    => CPU_Clock_Frequency, -- HZ
    VGA_CLK_FREQ           => VGA_CLK_FREQ, -- 25MHZ
      VGA_CLOCK_FREQUENCY    => PIX_Clock_Frequency, -- HZ
    VGA_HOR_CHARS          => 80, -- CHARACTERS 25.6us
           VGA_HOR_CHARS          => 80, -- CHARACTERS
    VGA_HOR_CHAR_PIXELS    => 8,  -- PIXELS 0.32us
           VGA_VER_CHARS          => 25, -- CHARACTERS
    VGA_HOR_FRONT_PORCH    => 16, -- PIXELS 0.64us
           VGA_PIXELS_PER_CHAR    => 8,  -- PIXELS
    VGA_HOR_SYNC           => 96, -- PIXELS 3.84us
           VGA_LINES_PER_CHAR     => 16, -- LINES
    VGA_HOR_BACK_PORCH     => 48, -- PIXELS 1.92us
           VGA_HOR_BACK_PORCH     => 40, -- PIXELS
    VGA_VER_CHARS          => 25, -- CHARACTERS 12.8ms
           VGA_HOR_SYNC           => 96, -- PIXELS
    VGA_VER_CHAR_LINES     => 16, -- LINES 0.512ms
           VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
    VGA_VER_FRONT_PORCH    => 10, -- LINES 0.320ms
           VGA_VER_BACK_PORCH     => 13, -- LINES
    VGA_VER_SYNC           => 2,  -- LINES 0.064ms
           VGA_VER_SYNC           => 1,  -- LINES
    VGA_VER_BACK_PORCH     => 34  -- LINES 1.088ms
           VGA_VER_FRONT_PORCH    => 36  -- LINES
 
  )
  )
  port map(
  port map(
 
 
                -- Control Registers
    -- CPU Control Registers interface
                vdu_clk       => cpu_clk,                                        -- 12.5 MHz System Clock in
                vdu_clk       => cpu_clk,                                        -- 12.5 MHz System Clock in
      vdu_rst       => cpu_reset,
    vdu_rst       => cpu_rst,
                vdu_cs        => vdu_cs,
                vdu_cs        => vdu_cs,
                vdu_rw        => cpu_rw,
                vdu_rw        => cpu_rw,
                vdu_addr      => cpu_addr(2 downto 0),
                vdu_addr      => cpu_addr(2 downto 0),
                vdu_data_in   => cpu_data_out,
                vdu_data_in   => cpu_data_out,
                vdu_data_out  => vdu_data_out,
                vdu_data_out  => vdu_data_out,
 
 
      -- vga port connections
      -- vga port connections
      vga_clk       => pix_clk,                                  -- 25 MHz VDU pixel clock
    vga_clk       => vga_clk,                                    -- 25 MHz VDU pixel clock
      vga_red_o     => vga_red,
    vga_red_o     => vga_red_o,
      vga_green_o   => vga_green,
    vga_green_o   => vga_green_o,
      vga_blue_o    => vga_blue,
    vga_blue_o    => vga_blue_o,
      vga_hsync_o   => h_drive,
    vga_hsync_o   => vga_hsync,
      vga_vsync_o   => v_drive
    vga_vsync_o   => vga_vsync
   );
   );
 
 
----------------------------------------
----------------------------------------
--
--
-- Timer Module
-- Timer Module
--
--
----------------------------------------
----------------------------------------
my_timer  : timer port map (
my_timer  : timer port map (
    clk       => cpu_clk,
    clk       => cpu_clk,
         rst       => cpu_reset,
    rst       => cpu_rst,
    cs        => timer_cs,
    cs        => timer_cs,
         rw        => cpu_rw,
         rw        => cpu_rw,
    addr      => cpu_addr(0),
    addr      => cpu_addr(0),
         data_in   => cpu_data_out,
         data_in   => cpu_data_out,
         data_out  => timer_data_out,
         data_out  => timer_data_out,
    irq       => timer_irq,
    irq       => timer_irq
         timer_in  => CountL(5),
 
         timer_out => timer_out
 
    );
    );
 
 
----------------------------------------
----------------------------------------
--
--
-- Bus Trap Interrupt logic
-- Bus Trap Interrupt logic
--
--
----------------------------------------
----------------------------------------
my_trap : trap port map (
my_trap : trap port map (
    clk        => cpu_clk,
    clk        => cpu_clk,
    rst        => cpu_reset,
    rst        => cpu_rst,
    cs         => trap_cs,
    cs         => trap_cs,
    rw         => cpu_rw,
    rw         => cpu_rw,
    vma        => cpu_vma,
    vma        => cpu_vma,
    addr       => cpu_addr,
    addr       => cpu_addr,
    data_in    => cpu_data_out,
    data_in    => cpu_data_out,
Line 750... Line 954...
--
--
-- Bus Trace logic
-- Bus Trace logic
--
--
----------------------------------------
----------------------------------------
--my_trace : trace port map (   
--my_trace : trace port map (   
--    clk           => SysClk,
--    clk           => sys_clk,
--    rst           => cpu_reset,
--    rst           => cpu_rst,
--    rs            => trace_cs,
--    rs            => trace_cs,
--    bs            => bank_cs,
--    bs            => bank_cs,
--    rw            => cpu_rw,
--    rw            => cpu_rw,
--    vma           => cpu_vma,
--    vma           => cpu_vma,
--    addr          => cpu_addr,
--    addr          => cpu_addr,
Line 764... Line 968...
--    buff_data_out => bank_data_out,
--    buff_data_out => bank_data_out,
--    cpu_data_in   => cpu_data_in,
--    cpu_data_in   => cpu_data_in,
--    irq           => trace_irq
--    irq           => trace_irq
--    );
--    );
 
 
 
 
----------------------------------------
----------------------------------------
--
--
-- Parallel I/O Port
-- Simple Parallel Port
--
--
----------------------------------------
----------------------------------------
my_ioport  : ioport port map (
my_spp  : spp port map (
 
    clk       => cpu_clk,
 
    rst       => cpu_rst,
 
    cs        => spp_cs,
 
    rw        => cpu_rw,
 
    addr      => cpu_addr(2 downto 0),
 
    data_in   => cpu_data_out,
 
    data_out  => spp_data_out,
 
    spp_data  => pp_data,
 
    spp_stat  => pp_stat,
 
    spp_ctrl  => pp_ctrl,
 
    hold      => open,
 
    irq       => open
 
  );
 
 
 
------------------------------------------------
 
--
 
-- 16 bit Peripheral Bus interface ($E100-$E1FF)
 
--
 
------------------------------------------------
 
my_pb : peripheral_bus port map (
 
    --
 
    -- CPU Interface signals
 
    --
         clk       => cpu_clk,
         clk       => cpu_clk,
    rst       => cpu_reset,
    rst       => cpu_rst,
    cs        => ioport_cs,
    cs        => pb_cs,
 
    addr      => cpu_addr(7 downto 0),
    rw        => cpu_rw,
    rw        => cpu_rw,
    addr      => cpu_addr(1 downto 0),
 
    data_in   => cpu_data_out,
    data_in   => cpu_data_out,
         data_out  => ioport_data_out,
    data_out  => pb_data_out,
         porta_io  => porta,
    hold      => pb_hold,
         portb_io  => portb
    --
 
    -- Peripheral Bus Interface Signals
 
    -- IO + ($00 - $FF) 
 
    --
 
    pb_rd_n   => pb_iord_n,
 
    pb_wr_n   => pb_iowr_n,
 
    pb_addr(2 downto 0) => pb_addr,
 
    pb_addr(4 downto 3) => open,
 
    pb_data   => pb_data,
 
 
 
    -- Peripheral chip selects on Peripheral Bus 
 
    ide_cs    => ide_cs,
 
    eth_cs    => ether_cs,
 
    sl1_cs    => slot1_cs,
 
    sl2_cs    => slot2_cs
         );
         );
 
 
 
------------------------------------------------------
--
--
-- 12.5 MHz CPU clock
-- External Bus interface Dual port RAM ($E200 - $EFFF)
--
--
cpu_clk_buffer : BUFG port map(
-------------------------------------------------------
    i => clock_div(1),
my_dpr : RAMB4_S8_S8 port map (
         o => cpu_clk
  RSTA  => cpu_rst,
 
  CLKA  => cpu_clk,
 
  ENA   => dpr_cs,
 
  WEA   => dpr_wr,
 
  ADDRA => cpu_addr(8 downto 0),
 
  DIA   => cpu_data_out,
 
  DOA   => dpr_data_out,
 
  RSTB  => cpu_rst,
 
  CLKB  => bus_gclk,
 
  ENB   => bus_cs,
 
  WEB   => bus_wr,
 
  ADDRB => bus_addr(8 downto 0),
 
  DIB   => bus_data_in,
 
  DOB   => bus_data_out
    );
    );
 
 
 
my_dpr_ibuf : IBUF port map (
 
  I     => bus_clk,
 
  O     => bus_iclk
 
  );
 
 
 
my_dpr_bufg : BUFG port map (
 
  I     => bus_iclk,
 
  O     => bus_gclk
 
  );
 
 
 
-----------------------------------------------
 
--
 
-- BED SRAM interface (256KBytes) ($0000-$DFFF)
--
--
-- 25 MHz VGA Pixel clock
-----------------------------------------------
 
my_bed_sram : BED_SRAM port map (
--
--
vga_clk_buffer : BUFG port map(
    -- CPU Interface signals
    i => clock_div(0),
    --
         o => pix_clk
    clk       => vga_clk,                        -- VGA Clock (twice the CPU clock)
 
    rst       => cpu_rst,                        -- Reset input (active high)
 
    cs        => ram_cs,                         -- RAM Chip Select
 
    addr(17 downto 12) => dat_addr( 5 downto 0), -- High RAM address goes to the DAT
 
    addr(11 downto  0) => cpu_addr(11 downto 0), -- Low RAM address goes to the CPU
 
    rw        => cpu_rw,                         -- Read / Not Write
 
    data_in   => cpu_data_out,                   -- Data Bus In 
 
    data_out  => ram_data_out,                   -- Data Bus Out
 
    --
 
    -- B3_SRAM Interface Signals
 
    --
 
    ram_csn   => ram_csn,
 
    ram_wrln  => ram_wrln,
 
    ram_wrun  => ram_wrun,
 
    ram_addr  => ram_addr,
 
    ram_data  => ram_data
    );
    );
 
 
----------------------------------------------------------------------
----------------------------------------------------------------------
--
--
-- Process to decode memory map
-- Process to decode memory map
--
--
----------------------------------------------------------------------
----------------------------------------------------------------------
 
 
mem_decode: process( cpu_clk, Reset_n, dat_addr,
my_decoder: process( cpu_addr, cpu_rw, cpu_vma,
                     cpu_addr, cpu_rw, cpu_vma,
                     dat_addr,
                                              rom_data_out,
                                              rom_data_out,
                                                        ram_data_out,
                     acia_data_out,
--                                            cf_data_out,
                     kbd_data_out,
 
                     vdu_data_out,
                                                   timer_data_out,
                                                   timer_data_out,
                                                        trap_data_out,
                                                        trap_data_out,
                                                        ioport_data_out,
                     spp_data_out,
                                                   uart_data_out,
                     dpr_data_out,
                                                        keyboard_data_out,
                     pb_data_out,
                                                        vdu_data_out,
                     ram_data_out )
--                                                      trace_data_out, 
 
                                                        bus_data )
 
variable decode_addr : std_logic_vector(4 downto 0);
 
begin
begin
    decode_addr := dat_addr(3 downto 0) & cpu_addr(11);
   cpu_data_in <= (others=>'0');
--    decode_addr := cpu_addr(15 downto 11);
   dat_cs      <= '0';
 
   rom_cs      <= '0';
 
   acia_cs     <= '0';
 
   kbd_cs      <= '0';
 
   vdu_cs      <= '0';
 
   timer_cs    <= '0';
 
   trap_cs     <= '0';
 
   spp_cs      <= '0';
 
   dpr_cs      <= '0';
 
   pb_cs       <= '0';
 
   ram_cs      <= '0';
 
 
    if cpu_addr( 15 downto 8 ) = "11111111" then
    if cpu_addr( 15 downto 8 ) = "11111111" then
 
      --
 
      -- Dynamic Address Translation $FFF0 - $FFFF
 
      --
                        cpu_data_in <= rom_data_out;
                        cpu_data_in <= rom_data_out;
                        rom_cs      <= cpu_vma;              -- read ROM
 
                        dat_cs      <= cpu_vma;              -- write DAT
                        dat_cs      <= cpu_vma;              -- write DAT
                        ram_cs      <= '0';
      rom_cs      <= cpu_vma;              -- read  ROM
                        uart_cs     <= '0';
 
--                      cf_cs       <= '0';
   elsif (dat_addr(3 downto 0) = "1111") and (cpu_addr(11) = '1') then -- $XF800 - $XFFFF
                        timer_cs    <= '0';
 
                        trap_cs     <= '0';
 
                        ioport_cs   <= '0';
 
                        keyboard_cs <= '0';
 
                        vdu_cs      <= '0';
 
                        bus_cs      <= '0';
 
--                        trace_cs    <= '0';
 
         else
 
      case decode_addr is
 
           --
           --
                -- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
      -- Sys09Bug Monitor ROM $F000 - $FFFF
                --
                --
                when "11111" => -- $F800 - $FFFF
 
                   cpu_data_in <= rom_data_out;
                   cpu_data_in <= rom_data_out;
                        rom_cs      <= cpu_vma;              -- read ROM
      rom_cs      <= cpu_vma;
                        dat_cs      <= '0';
 
                        ram_cs      <= '0';
 
                        uart_cs     <= '0';
 
--                      cf_cs       <= '0';
 
                        timer_cs    <= '0';
 
                        trap_cs     <= '0';
 
                        ioport_cs   <= '0';
 
                        keyboard_cs <= '0';
 
                        vdu_cs      <= '0';
 
                        bus_cs      <= '0';
 
--                        trace_cs    <= '0';
 
 
 
 
   elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
      --
      --
                -- IO Devices $E000 - $E7FF
                -- IO Devices $E000 - $E7FF
                --
                --
                when "11100" => -- $E000 - $E7FF
      case cpu_addr(11 downto 8) is
                        rom_cs    <= '0';
 
                   dat_cs    <= '0';
      --
                        ram_cs    <= '0';
      -- SWTPC peripherals from $E000 to $E0FF
 
      --
 
      when "0000" =>
                   case cpu_addr(7 downto 4) is
                   case cpu_addr(7 downto 4) is
                        --
                        --
                        -- UART / ACIA $E000
         -- ACIA RS232 Console Port $E000 - $E00F
                        --
                        --
                        when "0000" => -- $E000
                        when "0000" => -- $E000
                     cpu_data_in <= uart_data_out;
            cpu_data_in <= acia_data_out;
                          uart_cs     <= cpu_vma;
            acia_cs     <= cpu_vma;
--                        cf_cs       <= '0';
 
                          timer_cs    <= '0';
 
                          trap_cs     <= '0';
 
                          ioport_cs   <= '0';
 
                          keyboard_cs <= '0';
 
                          vdu_cs      <= '0';
 
                          bus_cs      <= '0';
 
--                        trace_cs    <= '0';
 
 
 
                        --
                        --
                        -- WD1771 FDC sites at $E010-$E01F
         -- Reserved
 
         -- Floppy Disk Controller port $E010 - $E01F
                        --
                        --
 
         when "0001" => -- $E010
 
            null;
 
 
         --
         --
         -- Keyboard port $E020 - $E02F
         -- Keyboard port $E020 - $E02F
                        --
                        --
                        when "0010" => -- $E020
                        when "0010" => -- $E020
           cpu_data_in <= keyboard_data_out;
            cpu_data_in <= kbd_data_out;
                          uart_cs     <= '0';
            kbd_cs <= cpu_vma;
--                        cf_cs       <= '0';
 
           timer_cs    <= '0';
 
                          trap_cs     <= '0';
 
                          ioport_cs   <= '0';
 
                          keyboard_cs <= cpu_vma;
 
                          vdu_cs      <= '0';
 
                          bus_cs      <= '0';
 
--                        trace_cs    <= '0';
 
 
 
         --
         --
         -- VDU port $E030 - $E03F
         -- VDU port $E030 - $E03F
                        --
                        --
                        when "0011" => -- $E030
                        when "0011" => -- $E030
           cpu_data_in <= vdu_data_out;
           cpu_data_in <= vdu_data_out;
                          uart_cs     <= '0';
 
--                        cf_cs       <= '0';
 
           timer_cs    <= '0';
 
                          trap_cs     <= '0';
 
                          ioport_cs   <= '0';
 
                          keyboard_cs <= '0';
 
                          vdu_cs      <= cpu_vma;
                          vdu_cs      <= cpu_vma;
                          bus_cs      <= '0';
 
--                        trace_cs    <= '0';
 
 
 
 
 
         --
         --
                        -- Compact Flash $E040 - $E04F
         -- Reserved SWTPc MP-T Timer $E040 - $E04F
                        --
                        --
--                      when "0100" => -- $E040
         when "0100" => -- $E040
--           cpu_data_in <= cf_data_out;
            cpu_data_in <= (others=> '0');
--                        uart_cs     <= '0';
 
--           cf_cs       <= cpu_vma;
 
--                        timer_cs    <= '0';
 
--                        trap_cs     <= '0';
 
--                        ioport_cs   <= '0';
 
--                        keyboard_cs <= '0';
 
--                        vdu_cs      <= '0';
 
--                        bus_cs      <= '0';
 
--                        trace_cs    <= '0';
 
 
 
         --
         --
         -- Timer $E050 - $E05F
         -- Timer $E050 - $E05F
                        --
                        --
                        when "0101" => -- $E050
                        when "0101" => -- $E050
           cpu_data_in <= timer_data_out;
           cpu_data_in <= timer_data_out;
                          uart_cs     <= '0';
 
--                        cf_cs       <= '0';
 
           timer_cs    <= cpu_vma;
           timer_cs    <= cpu_vma;
                          trap_cs     <= '0';
 
                          ioport_cs   <= '0';
 
                          keyboard_cs <= '0';
 
                          vdu_cs      <= '0';
 
                          bus_cs      <= '0';
 
--                        trace_cs    <= '0';
 
 
 
         --
         --
         -- Bus Trap Logic $E060 - $E06F
         -- Bus Trap Logic $E060 - $E06F
                        --
                        --
--                      when "0110" => -- $E060
         when "0110" => -- $E060
--         cpu_data_in <= trap_data_out;
            cpu_data_in <= trap_data_out;
--                        uart_cs     <= '0';
            trap_cs     <= cpu_vma;
--         cf_cs       <= '0';
 
--         timer_cs    <= '0';
 
--         trap_cs     <= cpu_vma;
 
--         ioport_cs   <= '0';
 
--         keyboard_cs <= '0';
 
--         vdu_cs      <= '0';
 
--         bus_cs      <= '0';
 
--                        trace_cs    <= '0';
 
 
 
         --
 
         -- I/O port $E070 - $E07F
 
                        --
 
                        when "0111" => -- $E070
 
           cpu_data_in <= ioport_data_out;
 
                          uart_cs     <= '0';
 
--                        cf_cs       <= '0';
 
           timer_cs    <= '0';
 
                          trap_cs     <= '0';
 
                          ioport_cs   <= cpu_vma;
 
                          keyboard_cs <= '0';
 
                          vdu_cs      <= '0';
 
                          bus_cs      <= '0';
 
--                        trace_cs    <= '0';
 
 
 
         --
         --
         -- Bus Trace Logic $E0C00 - $E0CF
         -- Bus Trace Logic $E070 - $E07F
                        --
                        --
--                      when "1100" => -- $E0C0
--         when "0111" => -- $E070
--         cpu_data_in <= trace_data_out;
--         cpu_data_in <= trace_data_out;
--                        uart_cs     <= '0';
 
--                        keyboard_cs <= '0';
 
--         timer_cs    <= '0';
 
--                        vdu_cs      <= '0';
 
--                        ioport_cs   <= '0';
 
--                        cf_cs       <= '0';
 
--                        trap_cs     <= '0';
 
--                        trace_cs    <= cpu_vma;
--                        trace_cs    <= cpu_vma;
 
 
 
         --
 
         -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
 
         --
 
         when "1000" => -- $E080
 
            null;
 
 
 
         --
 
         -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
 
         --
 
 
 
         --
 
         -- Simple Parallel Port $E0A0 - $E0AF
 
         --
 
         when "1010" => -- $E0A0
 
            cpu_data_in <= spp_data_out;
 
            spp_cs      <= cpu_vma;
 
 
 
         --
 
         -- Remaining 5 slots reserved for non SWTPc Peripherals
 
         --
 
         when others => -- $E0B0 to $E0FF
 
            cpu_data_in <= (others=> '0');
 
 
                        when others => -- $E080 to $E7FF
 
           cpu_data_in <= bus_data;
 
                          uart_cs     <= '0';
 
--                        cf_cs       <= '0';
 
                          timer_cs    <= '0';
 
                          trap_cs     <= '0';
 
                          ioport_cs   <= '0';
 
                          keyboard_cs <= '0';
 
                          vdu_cs      <= '0';
 
                          bus_cs      <= cpu_vma;
 
--                        trace_cs    <= '0';
 
                   end case;
                   end case;
                --
                --
                -- Everything else is RAM
      -- XST-3.0 Peripheral Bus goes here
 
      -- $E100 to $E1FF
 
      -- Four devices
 
      -- IDE, Ethernet, Slot1, Slot2
 
      --
 
      when "0001" =>
 
         cpu_data_in <= pb_data_out;
 
         pb_cs       <= cpu_vma;
 
 
 
      --
 
      -- $E200 to $EFFF reserved for future use
                --
                --
                when others =>
                when others =>
                  cpu_data_in <= ram_data_out;
         cpu_data_in <= dpr_data_out;
                  rom_cs      <= '0';
         dpr_cs      <= cpu_vma;
                  dat_cs      <= '0';
 
                  ram_cs      <= cpu_vma;
 
                  uart_cs     <= '0';
 
--                cf_cs       <= '0';
 
                  timer_cs    <= '0';
 
                  trap_cs     <= '0';
 
                  ioport_cs   <= '0';
 
                  keyboard_cs <= '0';
 
                  vdu_cs      <= '0';
 
                  bus_cs      <= '0';
 
--                        trace_cs    <= '0';
 
                end case;
 
        end if;
 
end process;
 
 
 
 
      end case;
 
 
--
--
-- B5-SRAM Control
   -- Flex RAM $0C000 - $0DFFF
-- Processes to read and write memory based on bus signals
 
--
--
ram_process: process( cpu_clk, Reset_n,
-- elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
                      cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
--    cpu_data_in <= flex_data_out;
                                               dat_addr,
--    flex_cs     <= cpu_vma;
                      ram_cs, ram_wrl, ram_wru, ram_data_out )
 
begin
 
    ram_csn <= not( ram_cs and Reset_n );
 
         ram_wrl  <= (not cpu_addr(0)) and (not cpu_rw) and cpu_clk;
 
         ram_wrln <= not (ram_wrl);
 
    ram_wru  <= cpu_addr(0) and (not cpu_rw) and cpu_clk;
 
         ram_wrun <= not (ram_wru);
 
         ram_addr(16 downto 11) <= dat_addr(5 downto 0);
 
         ram_addr(10 downto 0) <= cpu_addr(11 downto 1);
 
 
 
    if ram_wrl = '1' then
 
                ram_data(7 downto 0) <= cpu_data_out;
 
         else
 
      ram_data(7 downto 0)  <= "ZZZZZZZZ";
 
         end if;
 
 
 
         if ram_wru = '1' then
   --
                ram_data(15 downto 8) <= cpu_data_out;
   -- Everything else is RAM
 
   --
         else
         else
      ram_data(15 downto 8)  <= "ZZZZZZZZ";
      cpu_data_in <= ram_data_out;
 
      ram_cs      <= cpu_vma;
    end if;
    end if;
 
 
         if cpu_addr(0) = '1' then
 
      ram_data_out <= ram_data(15 downto 8);
 
         else
 
      ram_data_out <= ram_data(7 downto 0);
 
    end if;
 
end process;
end process;
 
 
--
--
-- Compact Flash Control
-- IDE drive / CF card signals ($E100 - $E13F)
 
-- Located on peripheral bus
--
--
--compact_flash: process( Reset_n,
ide_bus: process( cpu_rst, cpu_addr, ide_cs )
--                 cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
 
--                                        cf_cs, cf_rd, cf_wr, cf_d )
 
--begin
 
--       cf_rst_n  <= Reset_n;
 
--       cf_cs0_n  <= not( cf_cs ) or cpu_addr(3);
 
--       cf_cs1_n  <= not( cf_cs and cpu_addr(3));
 
--       cf_cs16_n <= '1';
 
--       cf_wr     <= cf_cs and (not cpu_rw);
 
--       cf_rd     <= cf_cs and cpu_rw;
 
--       cf_wr_n   <= not cf_wr;
 
--       cf_rd_n   <= not cf_rd;
 
--       cf_a      <= cpu_addr(2 downto 0);
 
--       if cf_wr = '1' then
 
--         cf_d(7 downto 0) <= cpu_data_out;
 
--       else
 
--         cf_d(7 downto 0) <= "ZZZZZZZZ";
 
--       end if;
 
--       cf_data_out <= cf_d(7 downto 0);
 
--       cf_d(15 downto 8) <= "ZZZZZZZZ";
 
--end process;
 
 
 
--
 
-- Hold CF access       for a few cycles
 
--
 
--cf_hold_proc: process( cpu_clk, Reset_n )
 
--begin
 
--    if Reset_n = '0' then
 
--               cf_release    <= '0';
 
--               cf_count      <= "0000";
 
--          cf_hold_state <= hold_release_state;
 
--       elsif cpu_clk'event and cpu_clk='0' then
 
--          case cf_hold_state is
 
--               when hold_release_state =>
 
--          cf_release <= '0';
 
--                  if cf_cs = '1' then
 
--                          cf_count      <= "0011";
 
--                               cf_hold_state <= hold_request_state;
 
--                       end if;
 
--
 
--               when hold_request_state =>
 
--                  cf_count <= cf_count - "0001";
 
--                       if cf_count = "0000" then
 
--             cf_release    <= '1';
 
--                               cf_hold_state <= hold_release_state;
 
--                       end if;
 
--       when others =>
 
--                  null;
 
--       end case;
 
--       end if;
 
--end process;
 
 
 
--
 
-- Interrupts and other bus control signals
 
--
 
interrupts : process( Reset_n,
 
--                                                       cf_cs, cf_hold, cf_release,
 
                      uart_irq,
 
                                                         trap_irq,
 
                      timer_irq, keyboard_irq
 
                                                         )
 
begin
begin
--    cf_hold   <= cf_cs and (not cf_release);
  ide_cs0_n    <= not( ide_cs ) or cpu_addr(4);
         cpu_reset <= not Reset_n; -- CPU reset is active high
  ide_cs1_n    <= not( ide_cs and cpu_addr(4));
    cpu_irq   <= uart_irq or keyboard_irq;
  ide_dmack_n  <= '1';
         cpu_nmi   <= trap_irq;
  ide_rst_n    <= not cpu_rst;
         cpu_firq  <= timer_irq;
  ide_con_csel <= '0';
         cpu_halt  <= '0';
  ide_dasp_n   <= not ide_cs;
--       cpu_hold  <= cf_hold;
 
         cpu_hold  <= '0';
 
end process;
 
 
 
--
 
-- CPU bus signals
 
--
 
my_bus : process( cpu_clk, cpu_reset, cpu_rw, cpu_addr, cpu_data_out, bus_cs )
 
begin
 
        bus_clk   <= cpu_clk;
 
   bus_reset <= cpu_reset;
 
        bus_rw    <= cpu_rw;
 
        bus_csn   <= not bus_cs;
 
   bus_addr  <= dat_addr(7 downto 0) & cpu_addr(11 downto 0);
 
        if( cpu_rw = '1' ) then
 
           bus_data <= "ZZZZZZZZ";
 
   else
 
           bus_data <= cpu_data_out;
 
   end if;
 
end process;
end process;
 
 
  --
  --
  -- flash led to indicate code is working
-- Assign CPU interface signals
  --
  --
my_LED_Flasher: process (cpu_clk, CountL )
cpu_controls : process( rst_n, pb_hold,
 
                        acia_irq, kbd_irq, trap_irq, timer_irq )
begin
begin
    if(cpu_clk'event and cpu_clk = '0') then
  cpu_rst  <= not rst_n; -- CPU reset is active high
      countL <= countL + 1;
  cpu_irq  <= acia_irq or kbd_irq;
    end if;
  cpu_nmi  <= trap_irq;
         LED <= countL(23);
  cpu_firq <= timer_irq;
         dcd_n <= '0';
  cpu_halt <= '0';
 
  cpu_hold <= pb_hold;
end process;
end process;
 
 
--
--
-- Clock divider
-- Assign DPR bus interface signals
--
--
my_clock_divider: process( SysClk )
my_dpr_bus : process( bus_cs_n, bus_rw, cpu_rw )
begin
begin
        if SysClk'event and SysClk='0' then
  bus_cs <= not bus_cs_n;
                clock_div <= clock_div + "01";
  bus_wr <= not bus_rw;
        end if;
  dpr_wr <= not cpu_rw;
 
--  trace_data_out <= (others=>'0');
end process;
end process;
 
 
--
--
-- Assign VDU VGA colour output
-- Assign VDU VGA output signals
-- only 8 colours are handled.
-- only 8 colours are handled.
--
--
my_vga_out: process( vga_red, vga_green, vga_blue )
my_vga_out: process( vga_red_o, vga_green_o, vga_blue_o )
begin
begin
           red_lo   <= vga_red;
  vga_red(0)   <= vga_red_o;
      red_hi   <= vga_red;
  vga_red(1)   <= vga_red_o;
      green_lo <= vga_green;
  vga_green(0) <= vga_green_o;
      green_hi <= vga_green;
  vga_green(1) <= vga_green_o;
      blue_lo  <= vga_blue;
  vga_blue(0)  <= vga_blue_o;
      blue_hi  <= vga_blue;
  vga_blue(1)  <= vga_blue_o;
end process;
end process;
 
 
end rtl; --===================== End of architecture =======================--
end rtl; --===================== End of architecture =======================--
 
 
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