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[/] [System09/] [trunk/] [rtl/] [System09_BurchED_B5-X300/] [System09_BurchED_B5-X300.ucf] - Diff between revs 66 and 108

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Rev 66 Rev 108
Line 1... Line 1...
#### UCF file created by Project Navigator
#### UCF file created by Project Navigator
#
#
NET "reset_n"      LOC = "p57" ;
NET "rst_n"        LOC = "p57" ;
NET "sysclk"       LOC = "p77" ;
NET "clk_in"       LOC = "p77" ;
#
#
# For B5-Compact-Flash:
# For B5-Compact-Flash:
# Connector A
# Connector A
#
#
#NET "pin2"        LOC = "P3"  ; #J1-2
#NET "pin2"        LOC = "P3"  ; #J1-2
Line 159... Line 159...
#NET "pin5"        LOC = "p188"; #pin 5
#NET "pin5"        LOC = "p188"; #pin 5
#NET "pin6"        LOC = "p189"; #pin 6
#NET "pin6"        LOC = "p189"; #pin 6
#NET "pin7"        LOC = "p191"; #pin 7
#NET "pin7"        LOC = "p191"; #pin 7
#NET "pin8"        LOC = "p192"; #pin 8
#NET "pin8"        LOC = "p192"; #pin 8
#NET "pin9"        LOC = "p193"; #pin 9
#NET "pin9"        LOC = "p193"; #pin 9
NET "timer_out"     LOC = "p194"; #pin 10
#NET "pin10"     LOC = "p194"; #pin 10
NET "bus_data<0>"   LOC = "p198"; #pin 11
NET "bus_data<0>"   LOC = "p198"; #pin 11
NET "bus_data<1>"   LOC = "p199"; #pin 12
NET "bus_data<1>"   LOC = "p199"; #pin 12
NET "bus_data<2>"   LOC = "p200"; #pin 13
NET "bus_data<2>"   LOC = "p200"; #pin 13
NET "bus_data<3>"   LOC = "p201"; #pin 14
NET "bus_data<3>"   LOC = "p201"; #pin 14
NET "bus_data<4>"   LOC = "p202"; #pin 15
NET "bus_data<4>"   LOC = "p202"; #pin 15
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INST "ram_wrun" TNM = "gram_wr";
INST "ram_wrun" TNM = "gram_wr";
INST "ram_csn" TNM = "gram_cs";
INST "ram_csn" TNM = "gram_cs";
#
#
# Timing Constraints
# Timing Constraints
#
#
#TIMEGRP "gram_cs"   OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_cs"   OFFSET = OUT 40 ns AFTER "clk_in";
#TIMEGRP "gram_wr"   OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_wr"   OFFSET = OUT 40 ns AFTER "clk_in";
#TIMEGRP "gram_addr" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_addr" OFFSET = OUT 40 ns AFTER "clk_in";
#TIMEGRP "gram_data" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_data" OFFSET = OUT 40 ns AFTER "clk_in";
#TIMEGRP "gram_data" OFFSET = IN 15 ns BEFORE "sysclk";
#TIMEGRP "gram_data" OFFSET = IN 15 ns BEFORE "clk_in";
#TIMEGRP "gtest_alu" OFFSET = OUT 90 ns AFTER "sysclk";
#TIMEGRP "gtest_alu" OFFSET = OUT 90 ns AFTER "clk_in";
#TIMEGRP "gtest_cc"  OFFSET = OUT 95 ns AFTER "sysclk";
#TIMEGRP "gtest_cc"  OFFSET = OUT 95 ns AFTER "clk_in";
NET "sysclk" TNM_NET = "sysclk";
NET "clk_in" TNM_NET = "clk_in";
TIMESPEC "TS_sysclk" = PERIOD "sysclk" 20 ns LOW 50 %;
TIMESPEC "TS_clk_in" = PERIOD "clk_in" 20 ns LOW 50 %;
#
#
# Fast I/O Pins
# Fast I/O Pins
#
#
NET "ram_csn" FAST;
NET "ram_csn" FAST;
NET "ram_wrln" FAST;
NET "ram_wrln" FAST;

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