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--===========================================================================----
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--===========================================================================
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--
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--
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-- S Y N T H E Z I A B L E System09 - SOC.
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-- System09 - SoC for the BurchED B5-X300 Spartan2 FPGA board.
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--
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--
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-- www.OpenCores.Org - September 2003
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--===========================================================================
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-- This core adheres to the GNU public license
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--
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--
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-- File name : System09_BurchED_B5-X300.vhd
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-- File name : System09_BurchED_B5-X300.vhd
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--
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--
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-- Entity name : my_system09
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--
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-- Purpose : Top level file for 6809 compatible system on a chip
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-- Purpose : Top level file for 6809 compatible system on a chip
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-- Designed with Xilinx XC2S300e Spartan 2+ FPGA.
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-- Designed with Xilinx XC2S300e Spartan 2+ FPGA.
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-- Implemented With BurchED B5-X300 FPGA board,
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-- Implemented With BurchED B5-X300 FPGA board,
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-- B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module
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-- B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module
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--
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--
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-- Dependencies : ieee.Std_Logic_1164
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-- Dependencies : ieee.Std_Logic_1164
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_arith
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-- ieee.std_logic_arith
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-- ieee.numeric_std
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-- ieee.numeric_std
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--
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--
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-- Uses :
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-- Uses : clock_div (../vhdl/clock_div.vhd) System clock divider
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-- cpu09 (cpu09.vhd) CPU core
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-- flasher (../vhdl/flasher.vhd) LED flasher
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-- SYS09BUG_F800 (sys09b5x_b4.vhd) Monitor ROM
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-- BED_SRAM (../vhdl/BED_SRAM.vhd) BurchED SRAM interface
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-- dat_ram (datram.vhd) Dynamic Address Translation
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-- cpu09 (../vhdl/cpu09.vhd) CPU core
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-- acia6850 (acia6850.vhd) ACIA / MiniUART
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-- SYS09BUG_F800 (../spartan2/sys09b5x_b4.vhd) Monitor ROM
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-- ACIA_Clock (ACIA_Clock.vhd) ACIA Baud Clock Divider
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-- dat_ram (../vhdl/datram.vhd) Dynamic Address Translation
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-- keyboard (keyboard.vhd) PS/2 Keyboard Interface
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-- acia6850 (../vhdl/acia6850.vhd) ACIA
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-- vdu8 (vdu8.vhd) 80 x 25 Video Display
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-- ACIA_Clock (../vhdl/ACIA_Clock.vhd) ACIA Baud Clock Divider
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-- timer (timer.vhd) Timer module
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-- keyboard (../vhdl/keyboard.vhd) PS/2 Keyboard Interface
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-- trap (trap.vhd) Bus Trap interrupt
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-- vdu8 (../vhdl/vdu8.vhd) 80 x 25 Video Display
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-- ioport (ioport.vhd) Parallel I/O port.
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-- timer (../vhdl/timer.vhd) Timer module
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-- trap (../vhdl/trap.vhd) Bus Trap interrupt
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-- ioport (../vhdl/ioport.vhd) Parallel I/O port.
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--
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--
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-- Author : John E. Kent
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-- Author : John E. Kent
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-- dilbert57@opencores.org
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-- dilbert57@opencores.org
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-- Memory Map :
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-- Memory Map :
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-- Memory Map :
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--
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--
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-- $0000 - $DFFF System RAM (256K Mapped via DAT)
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-- $0000 - $DFFF System RAM (256K Mapped via DAT)
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-- $E000 - ACIA (SWTPc)
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-- $E000 - ACIA (SWTPc)
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-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
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-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
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-- $E020 - Keyboard
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-- $E020 - Keyboard
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-- $E200 - $EFFF Dual Port RAM interface
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-- $E200 - $EFFF Dual Port RAM interface
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-- $F000 - $F7FF Reserved SWTPc DMAF-2
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-- $F000 - $F7FF Reserved SWTPc DMAF-2
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-- $F800 - $FFFF Sys09bug ROM (Read only)
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-- $F800 - $FFFF Sys09bug ROM (Read only)
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-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
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-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
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--
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--
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--===========================================================================----
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--
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-- Copyright (C) 2003 - 2010 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================
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--
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--
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-- Revision History:
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-- Revision History:
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--===========================================================================--
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--
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--===========================================================================
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-- Version 0.1 - 20 March 2003
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-- Version 0.1 - 20 March 2003
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-- Version 0.2 - 30 March 2003
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-- Version 0.2 - 30 March 2003
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-- Version 0.3 - 29 April 2003
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-- Version 0.3 - 29 April 2003
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-- Version 0.4 - 29 June 2003
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-- Version 0.4 - 29 June 2003
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--
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--
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library unisim;
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library unisim;
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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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entity System09 is
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entity my_system09 is
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port(
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port(
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clk_in : in Std_Logic; -- System Clock input
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clk_in : in Std_Logic; -- System Clock input
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rst_n : in Std_logic; -- Master Reset input (active low)
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rst_n : in Std_logic; -- Master Reset input (active low)
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LED : out std_logic; -- Diagnostic LED Flasher
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LED : out std_logic; -- Diagnostic LED Flasher
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bus_rw : out std_logic;
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bus_rw : out std_logic;
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bus_cs : out std_logic;
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bus_cs : out std_logic;
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bus_addr : out std_logic_vector(15 downto 0);
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bus_addr : out std_logic_vector(15 downto 0);
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bus_data : inout std_logic_vector(7 downto 0)
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bus_data : inout std_logic_vector(7 downto 0)
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);
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);
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end System09;
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end my_system09;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for System09
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-- Architecture for System09
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture rtl of System09 is
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architecture rtl of my_system09 is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- constants
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-- constants
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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constant SYS_CLK_FREQ : integer := 50000000; -- FPGA System Clock
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constant SYS_CLK_FREQ : integer := 50000000; -- FPGA System Clock
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constant VGA_CLK_FREQ : integer := 25000000; -- VGA Pixel Clock
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constant VGA_CLK_FREQ : integer := 25000000; -- VGA Pixel Clock
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