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[/] [System09/] [trunk/] [rtl/] [System09_BurchED_B5-X300/] [System09_BurchED_B5-X300.vhd] - Diff between revs 108 and 119

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--===========================================================================----
--===========================================================================
--
--
--  S Y N T H E Z I A B L E    System09 - SOC.
--  System09 - SoC for the BurchED B5-X300 Spartan2 FPGA board.
--
--
--  www.OpenCores.Org - September 2003
--===========================================================================
--  This core adheres to the GNU public license  
 
--
--
-- File name      : System09_BurchED_B5-X300.vhd
-- File name      : System09_BurchED_B5-X300.vhd
--
--
 
-- Entity name    : my_system09
 
--
-- Purpose        : Top level file for 6809 compatible system on a chip
-- Purpose        : Top level file for 6809 compatible system on a chip
--                  Designed with Xilinx XC2S300e Spartan 2+ FPGA.
--                  Designed with Xilinx XC2S300e Spartan 2+ FPGA.
--                  Implemented With BurchED B5-X300 FPGA board,
--                  Implemented With BurchED B5-X300 FPGA board,
--                  B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module
--                  B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module
--
--
-- Dependencies   : ieee.Std_Logic_1164
-- Dependencies   : ieee.Std_Logic_1164
--                  ieee.std_logic_unsigned
--                  ieee.std_logic_unsigned
--                  ieee.std_logic_arith
--                  ieee.std_logic_arith
--                  ieee.numeric_std
--                  ieee.numeric_std
--
--
-- Uses           : 
-- Uses           : clock_div     (../vhdl/clock_div.vhd)       System clock divider
--                  cpu09         (cpu09.vhd)      CPU core
--                  flasher       (../vhdl/flasher.vhd)         LED flasher
--                  SYS09BUG_F800 (sys09b5x_b4.vhd) Monitor ROM
--                  BED_SRAM      (../vhdl/BED_SRAM.vhd)        BurchED SRAM interface
--                  dat_ram       (datram.vhd)     Dynamic Address Translation
--                  cpu09         (../vhdl/cpu09.vhd)           CPU core
--                  acia6850      (acia6850.vhd) ACIA / MiniUART
--                  SYS09BUG_F800 (../spartan2/sys09b5x_b4.vhd) Monitor ROM
--                  ACIA_Clock    (ACIA_Clock.vhd) ACIA Baud Clock Divider
--                  dat_ram       (../vhdl/datram.vhd)          Dynamic Address Translation
--                  keyboard      (keyboard.vhd)   PS/2 Keyboard Interface
--                  acia6850      (../vhdl/acia6850.vhd)        ACIA
--                  vdu8          (vdu8.vhd)       80 x 25 Video Display
--                  ACIA_Clock    (../vhdl/ACIA_Clock.vhd)      ACIA Baud Clock Divider
--                  timer         (timer.vhd)      Timer module
--                  keyboard      (../vhdl/keyboard.vhd)        PS/2 Keyboard Interface
--                  trap               (trap.vhd)       Bus Trap interrupt
--                  vdu8          (../vhdl/vdu8.vhd)            80 x 25 Video Display
--                  ioport        (ioport.vhd)     Parallel I/O port.
--                  timer         (../vhdl/timer.vhd)           Timer module
 
--                  trap               (../vhdl/trap.vhd)            Bus Trap interrupt
 
--                  ioport        (../vhdl/ioport.vhd)          Parallel I/O port.
-- 
-- 
-- Author         : John E. Kent      
-- Author         : John E. Kent      
--                  dilbert57@opencores.org      
--                  dilbert57@opencores.org      
--      Memory Map     :
--      Memory Map     :
-- Memory Map     :
 
--
--
-- $0000 - $DFFF System RAM (256K Mapped via DAT)
-- $0000 - $DFFF System RAM (256K Mapped via DAT)
-- $E000 - ACIA (SWTPc)
-- $E000 - ACIA (SWTPc)
-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
-- $E020 - Keyboard
-- $E020 - Keyboard
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-- $E200 - $EFFF Dual Port RAM interface
-- $E200 - $EFFF Dual Port RAM interface
-- $F000 - $F7FF Reserved SWTPc DMAF-2
-- $F000 - $F7FF Reserved SWTPc DMAF-2
-- $F800 - $FFFF Sys09bug ROM (Read only)
-- $F800 - $FFFF Sys09bug ROM (Read only)
-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
--
--
--===========================================================================----
--
 
--  Copyright (C) 2003 - 2010 John Kent
 
--
 
--  This program is free software: you can redistribute it and/or modify
 
--  it under the terms of the GNU General Public License as published by
 
--  the Free Software Foundation, either version 3 of the License, or
 
--  (at your option) any later version.
 
--
 
--  This program is distributed in the hope that it will be useful,
 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 
--  GNU General Public License for more details.
 
--
 
--  You should have received a copy of the GNU General Public License
 
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
--
 
--===========================================================================
--
--
-- Revision History:
-- Revision History:
--===========================================================================--
--
 
--===========================================================================
-- Version 0.1 - 20 March 2003
-- Version 0.1 - 20 March 2003
-- Version 0.2 - 30 March 2003
-- Version 0.2 - 30 March 2003
-- Version 0.3 - 29 April 2003
-- Version 0.3 - 29 April 2003
-- Version 0.4 - 29 June 2003
-- Version 0.4 - 29 June 2003
--
--
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   use IEEE.STD_LOGIC_UNSIGNED.ALL;
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
   use ieee.numeric_std.all;
   use ieee.numeric_std.all;
library unisim;
library unisim;
        use unisim.vcomponents.all;
        use unisim.vcomponents.all;
 
 
entity System09 is
entity my_system09 is
  port(
  port(
    clk_in      : in  Std_Logic;  -- System Clock input
    clk_in      : in  Std_Logic;  -- System Clock input
         rst_n       : in  Std_logic;  -- Master Reset input (active low)
         rst_n       : in  Std_logic;  -- Master Reset input (active low)
    LED         : out std_logic;  -- Diagnostic LED Flasher
    LED         : out std_logic;  -- Diagnostic LED Flasher
 
 
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         bus_rw       : out std_logic;
         bus_rw       : out std_logic;
         bus_cs       : out std_logic;
         bus_cs       : out std_logic;
    bus_addr     : out std_logic_vector(15 downto 0);
    bus_addr     : out std_logic_vector(15 downto 0);
         bus_data     : inout std_logic_vector(7 downto 0)
         bus_data     : inout std_logic_vector(7 downto 0)
         );
         );
end System09;
end my_system09;
 
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Architecture for System09
-- Architecture for System09
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture rtl of System09 is
architecture rtl of my_system09 is
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- constants
  -- constants
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  constant SYS_CLK_FREQ  : integer := 50000000;  -- FPGA System Clock
  constant SYS_CLK_FREQ  : integer := 50000000;  -- FPGA System Clock
  constant VGA_CLK_FREQ  : integer := 25000000;  -- VGA Pixel Clock
  constant VGA_CLK_FREQ  : integer := 25000000;  -- VGA Pixel Clock

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