| Line 155... |
Line 155... |
use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
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entity my_system09 is
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entity system09 is
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port(
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port(
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sys_clk : in Std_Logic; -- System Clock input
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sys_clk : in Std_Logic; -- System Clock input
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rst_sw : in Std_logic; -- Master Reset input (active high)
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rst_sw : in Std_logic; -- Master Reset input (active high)
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nmi_sw : in Std_logic;
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nmi_sw : in Std_logic;
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|
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| Line 199... |
Line 199... |
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-- seven segment display
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-- seven segment display
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segments : out std_logic_vector(7 downto 0);
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segments : out std_logic_vector(7 downto 0);
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digits : out std_logic_vector(3 downto 0)
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digits : out std_logic_vector(3 downto 0)
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);
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);
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end my_system09;
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end system09;
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|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for System09
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-- Architecture for System09
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture my_computer of my_system09 is
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architecture my_computer of system09 is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- constants
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-- constants
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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constant SYS_CLK_FREQ : integer := 50000000; -- FPGA System Clock
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constant SYS_CLK_FREQ : integer := 50000000; -- FPGA System Clock
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constant VGA_CLK_FREQ : integer := 25000000; -- VGA Pixel Clock
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constant VGA_CLK_FREQ : integer := 25000000; -- VGA Pixel Clock
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