| Line 1... |
Line 1... |
-- $Id: System09_Digilent_3S500E.vhd,v 1.4 2008-08-20 06:00:55 davidgb Exp $
|
-- $Id: System09_Digilent_3S500E.vhd,v 1.3.2.1 2008/04/08 14:59:48 davidgb Exp $
|
--===========================================================================----
|
--===========================================================================----
|
--
|
--
|
-- S Y N T H E Z I A B L E System09 - SOC.
|
-- S Y N T H E Z I A B L E System09 - SOC.
|
--
|
--
|
|
--===========================================================================----
|
|
--
|
-- This core adheres to the GNU public license
|
-- This core adheres to the GNU public license
|
--
|
--
|
-- File name : System09.vhd
|
-- File name : System09_Digilent_3S500E.vhd
|
--
|
--
|
-- Purpose : Top level file for 6809 compatible system on a chip
|
-- Purpose : Top level file for 6809 compatible system on a chip
|
-- Designed with Xilinx XC3S500E Spartan 3E FPGA.
|
-- Designed with Xilinx XC3S500E Spartan 3E FPGA.
|
-- Implemented With Digilent Xilinx Starter FPGA board,
|
-- Implemented With Digilent Xilinx Starter FPGA board,
|
--
|
--
|
| Line 118... |
Line 120... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
architecture my_computer of my_system09 is
|
architecture my_computer of my_system09 is
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- constants
|
-- constants
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock
|
constant SYS_CLK_FREQ : integer := 50000000; -- FPGA System Clock
|
constant PIX_Clock_Frequency : integer := 25000000; -- VGA Pixel Clock
|
constant VGA_CLK_FREQ : integer := 25000000; -- VGA Pixel Clock
|
constant CPU_Clock_Frequency : integer := 25000000; -- CPU Clock
|
constant CPU_CLK_FREQ : integer := 25000000; -- CPU Clock
|
constant BAUD_Rate : integer := 57600; -- Baud Rate
|
constant BAUD_RATE : integer := 57600; -- Baud Rate
|
constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
|
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Signals
|
-- Signals
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- BOOT ROM
|
-- BOOT ROM
|
| Line 164... |
Line 166... |
signal keyboard_data_out : std_logic_vector(7 downto 0);
|
signal keyboard_data_out : std_logic_vector(7 downto 0);
|
signal keyboard_cs : std_logic;
|
signal keyboard_cs : std_logic;
|
signal keyboard_irq : std_logic;
|
signal keyboard_irq : std_logic;
|
|
|
-- Video Display Unit
|
-- Video Display Unit
|
signal pix_clk : std_logic;
|
signal vga_clk : std_logic;
|
signal vdu_cs : std_logic;
|
signal vdu_cs : std_logic;
|
signal vdu_data_out : std_logic_vector(7 downto 0);
|
signal vdu_data_out : std_logic_vector(7 downto 0);
|
|
|
-- RAM
|
-- RAM
|
signal ram_cs : std_logic; -- memory chip select
|
signal ram_cs : std_logic; -- memory chip select
|
| Line 202... |
Line 204... |
|
|
component cpu09
|
component cpu09
|
port (
|
port (
|
clk: in std_logic;
|
clk: in std_logic;
|
rst: in std_logic;
|
rst: in std_logic;
|
rw: out std_logic; -- Asynchronous memory interface
|
rw : out std_logic;
|
vma: out std_logic;
|
vma: out std_logic;
|
address: out std_logic_vector(15 downto 0);
|
address: out std_logic_vector(15 downto 0);
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data_in: in std_logic_vector(7 downto 0);
|
|
data_out: out std_logic_vector(7 downto 0);
|
data_out: out std_logic_vector(7 downto 0);
|
halt: in std_logic;
|
data_in : in std_logic_vector(7 downto 0);
|
hold: in std_logic;
|
|
irq: in std_logic;
|
irq: in std_logic;
|
nmi: in std_logic;
|
nmi: in std_logic;
|
firq: in std_logic
|
firq : in std_logic;
|
|
halt : in std_logic;
|
|
hold : in std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
----------------------------------------
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----------------------------------------
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| Line 228... |
Line 230... |
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (10 downto 0);
|
addr : in std_logic_vector (10 downto 0);
|
rdata : out std_logic_vector (7 downto 0);
|
data_in : in std_logic_vector (7 downto 0);
|
wdata : in std_logic_vector (7 downto 0)
|
data_out : out std_logic_vector (7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
| Line 245... |
Line 247... |
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (14 downto 0);
|
addr : in std_logic_vector (14 downto 0);
|
rdata : out std_logic_vector (7 downto 0);
|
data_in : in std_logic_vector (7 downto 0);
|
wdata : in std_logic_vector (7 downto 0)
|
data_out : out std_logic_vector (7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
| Line 283... |
Line 285... |
port (
|
port (
|
clk : in Std_Logic; -- System Clock
|
clk : in Std_Logic; -- System Clock
|
rst : in Std_Logic; -- Reset input (active high)
|
rst : in Std_Logic; -- Reset input (active high)
|
cs : in Std_Logic; -- miniUART Chip Select
|
cs : in Std_Logic; -- miniUART Chip Select
|
rw : in Std_Logic; -- Read / Not Write
|
rw : in Std_Logic; -- Read / Not Write
|
|
addr : in Std_Logic; -- Register Select
|
|
data_in : in Std_Logic_Vector(7 downto 0); -- Data Bus In
|
|
data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
|
irq : out Std_Logic; -- Interrupt
|
irq : out Std_Logic; -- Interrupt
|
Addr : in Std_Logic; -- Register Select
|
|
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
|
|
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
|
|
RxC : in Std_Logic; -- Receive Baud Clock
|
RxC : in Std_Logic; -- Receive Baud Clock
|
TxC : in Std_Logic; -- Transmit Baud Clock
|
TxC : in Std_Logic; -- Transmit Baud Clock
|
RxD : in Std_Logic; -- Receive Data
|
RxD : in Std_Logic; -- Receive Data
|
TxD : out Std_Logic; -- Transmit Data
|
TxD : out Std_Logic; -- Transmit Data
|
DCD_n : in Std_Logic; -- Data Carrier Detect
|
DCD_n : in Std_Logic; -- Data Carrier Detect
|
| Line 304... |
Line 306... |
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
|
|
component ACIA_Clock
|
component ACIA_Clock
|
generic (
|
generic (
|
SYS_Clock_Frequency : integer := SYS_Clock_Frequency;
|
SYS_CLK_FREQ : integer := SYS_CLK_FREQ;
|
ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
|
ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
|
);
|
);
|
port (
|
port (
|
clk : in Std_Logic; -- System Clock Input
|
clk : in Std_Logic; -- System Clock Input
|
ACIA_clk : out Std_logic -- ACIA Clock output
|
ACIA_clk : out Std_logic -- ACIA Clock output
|
);
|
);
|
| Line 329... |
Line 331... |
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic;
|
addr : in std_logic;
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
irq : out std_logic
|
irq : out std_logic
|
-- ;
|
|
-- timer_in : in std_logic;
|
|
-- timer_out : out std_logic
|
|
);
|
);
|
end component;
|
end component;
|
|
|
------------------------------------------------------------
|
------------------------------------------------------------
|
--
|
--
|
| Line 363... |
Line 362... |
--
|
--
|
----------------------------------------
|
----------------------------------------
|
|
|
component keyboard
|
component keyboard
|
generic(
|
generic(
|
KBD_Clock_Frequency : integer := CPU_Clock_Frequency
|
KBD_CLK_FREQ : integer := CPU_CLK_FREQ
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
| Line 386... |
Line 385... |
-- Video Display Unit.
|
-- Video Display Unit.
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
component vdu8
|
component vdu8
|
generic(
|
generic(
|
VDU_CLOCK_FREQUENCY : integer := CPU_Clock_Frequency; -- HZ
|
VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- 25MHz
|
VGA_CLOCK_FREQUENCY : integer := PIX_Clock_Frequency; -- HZ
|
VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us
|
VGA_HOR_CHARS : integer := 80; -- CHARACTERS
|
VGA_HOR_CHAR_PIXELS : integer := 8; -- PIXELS 0.32us
|
VGA_VER_CHARS : integer := 25; -- CHARACTERS
|
VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us (0.94us)
|
VGA_PIXELS_PER_CHAR : integer := 8; -- PIXELS
|
VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us (3.77us)
|
VGA_LINES_PER_CHAR : integer := 16; -- LINES
|
VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us (1.89us)
|
VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
|
VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms
|
VGA_HOR_SYNC : integer := 96; -- PIXELS
|
VGA_VER_CHAR_LINES : integer := 16; -- LINES 0.512ms
|
VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
|
VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms
|
VGA_VER_BACK_PORCH : integer := 13; -- LINES
|
VGA_VER_SYNC : integer := 2; -- LINES 0.064ms
|
VGA_VER_SYNC : integer := 1; -- LINES
|
VGA_VER_BACK_PORCH : integer := 34 -- LINES 1.088ms
|
VGA_VER_FRONT_PORCH : integer := 36 -- LINES
|
|
);
|
);
|
port(
|
port(
|
-- control register interface
|
-- control register interface
|
vdu_clk : in std_logic; -- CPU Clock - 12.5MHz
|
vdu_clk : in std_logic; -- CPU Clock - 12.5MHz
|
vdu_rst : in std_logic;
|
vdu_rst : in std_logic;
|
| Line 438... |
Line 436... |
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
vma => cpu_vma,
|
vma => cpu_vma,
|
address => cpu_addr(15 downto 0),
|
address => cpu_addr(15 downto 0),
|
data_in => cpu_data_in,
|
|
data_out => cpu_data_out,
|
data_out => cpu_data_out,
|
halt => cpu_halt,
|
data_in => cpu_data_in,
|
hold => cpu_hold,
|
|
irq => cpu_irq,
|
irq => cpu_irq,
|
nmi => cpu_nmi,
|
nmi => cpu_nmi,
|
firq => cpu_firq
|
firq => cpu_firq,
|
|
halt => cpu_halt,
|
|
hold => cpu_hold
|
);
|
);
|
|
|
my_rom : mon_rom port map (
|
my_rom : mon_rom port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => rom_cs,
|
cs => rom_cs,
|
rw => '1',
|
rw => '1',
|
addr => cpu_addr(10 downto 0),
|
addr => cpu_addr(10 downto 0),
|
rdata => rom_data_out,
|
data_in => cpu_data_out,
|
wdata => cpu_data_out
|
data_out => rom_data_out
|
);
|
);
|
|
|
my_ram : ram_32k port map (
|
my_ram : ram_32k port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => ram_cs,
|
cs => ram_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(14 downto 0),
|
addr => cpu_addr(14 downto 0),
|
rdata => ram_data_out,
|
data_in => cpu_data_out,
|
wdata => cpu_data_out
|
data_out => ram_data_out
|
);
|
);
|
|
|
my_pia : pia_timer port map (
|
my_pia : pia_timer port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
| Line 490... |
Line 488... |
my_ACIA : ACIA_6850 port map (
|
my_ACIA : ACIA_6850 port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => uart_cs,
|
cs => uart_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
|
addr => cpu_addr(0),
|
|
data_in => cpu_data_out,
|
|
data_out => uart_data_out,
|
irq => uart_irq,
|
irq => uart_irq,
|
Addr => cpu_addr(0),
|
|
Datain => cpu_data_out,
|
|
DataOut => uart_data_out,
|
|
RxC => uart_clk,
|
RxC => uart_clk,
|
TxC => uart_clk,
|
TxC => uart_clk,
|
RxD => rxbit,
|
RxD => rxbit,
|
TxD => txbit,
|
TxD => txbit,
|
DCD_n => dcd_n,
|
DCD_n => dcd_n,
|
| Line 510... |
Line 508... |
-- ACIA Clock
|
-- ACIA Clock
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_ACIA_Clock : ACIA_Clock
|
my_ACIA_Clock : ACIA_Clock
|
generic map(
|
generic map(
|
SYS_Clock_Frequency => SYS_Clock_Frequency,
|
SYS_CLK_FREQ => SYS_CLK_FREQ,
|
ACIA_Clock_Frequency => ACIA_Clock_Frequency
|
ACIA_CLK_FREQ => ACIA_CLK_FREQ
|
)
|
)
|
port map(
|
port map(
|
clk => SysClk,
|
clk => SysClk,
|
acia_clk => uart_clk
|
acia_clk => uart_clk
|
);
|
);
|
| Line 527... |
Line 525... |
-- PS/2 Keyboard Interface
|
-- PS/2 Keyboard Interface
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_keyboard : keyboard
|
my_keyboard : keyboard
|
generic map (
|
generic map (
|
KBD_Clock_Frequency => CPU_Clock_frequency
|
KBD_CLK_FREQ => CPU_CLK_FREQ
|
)
|
)
|
port map(
|
port map(
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => keyboard_cs,
|
cs => keyboard_cs,
|
| Line 549... |
Line 547... |
-- Video Display Unit instantiation
|
-- Video Display Unit instantiation
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_vdu : vdu8
|
my_vdu : vdu8
|
generic map(
|
generic map(
|
VDU_CLOCK_FREQUENCY => CPU_Clock_Frequency, -- HZ
|
VGA_CLK_FREQ => VGA_CLK_FREQ, -- HZ
|
VGA_CLOCK_FREQUENCY => PIX_Clock_Frequency, -- HZ
|
|
VGA_HOR_CHARS => 80, -- CHARACTERS
|
VGA_HOR_CHARS => 80, -- CHARACTERS
|
VGA_VER_CHARS => 25, -- CHARACTERS
|
VGA_HOR_CHAR_PIXELS => 8, -- PIXELS
|
VGA_PIXELS_PER_CHAR => 8, -- PIXELS
|
VGA_HOR_FRONT_PORCH => 16, -- PIXELS
|
VGA_LINES_PER_CHAR => 16, -- LINES
|
|
VGA_HOR_BACK_PORCH => 40, -- PIXELS
|
|
VGA_HOR_SYNC => 96, -- PIXELS
|
VGA_HOR_SYNC => 96, -- PIXELS
|
VGA_HOR_FRONT_PORCH => 24, -- PIXELS
|
VGA_HOR_BACK_PORCH => 48, -- PIXELS
|
VGA_VER_BACK_PORCH => 13, -- LINES
|
VGA_VER_CHARS => 25, -- CHARACTERS
|
VGA_VER_SYNC => 1, -- LINES
|
VGA_VER_CHAR_LINES => 16, -- LINES
|
VGA_VER_FRONT_PORCH => 36 -- LINES
|
VGA_VER_FRONT_PORCH => 10, -- LINES
|
|
VGA_VER_SYNC => 2, -- LINES
|
|
VGA_VER_FRONT_PORCH => 34 -- LINES
|
)
|
)
|
port map(
|
port map(
|
|
|
-- Control Registers
|
-- Control Registers
|
vdu_clk => cpu_clk, -- 25 MHz System Clock in
|
vdu_clk => cpu_clk, -- 25 MHz System Clock in
|
| Line 574... |
Line 571... |
vdu_addr => cpu_addr(2 downto 0),
|
vdu_addr => cpu_addr(2 downto 0),
|
vdu_data_in => cpu_data_out,
|
vdu_data_in => cpu_data_out,
|
vdu_data_out => vdu_data_out,
|
vdu_data_out => vdu_data_out,
|
|
|
-- vga port connections
|
-- vga port connections
|
vga_clk => pix_clk, -- 25 MHz VDU pixel clock
|
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
|
vga_red_o => vga_red,
|
vga_red_o => vga_red,
|
vga_green_o => vga_green,
|
vga_green_o => vga_green,
|
vga_blue_o => vga_blue,
|
vga_blue_o => vga_blue,
|
vga_hsync_o => vga_hsync,
|
vga_hsync_o => vga_hsync,
|
vga_vsync_o => vga_vsync
|
vga_vsync_o => vga_vsync
|
| Line 597... |
Line 594... |
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(0),
|
addr => cpu_addr(0),
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => timer_data_out,
|
data_out => timer_data_out,
|
irq => timer_irq
|
irq => timer_irq
|
-- ,
|
|
-- timer_in => CountL(5)
|
|
-- timer_out => timer_out
|
|
);
|
);
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Bus Trap Interrupt logic
|
-- Bus Trap Interrupt logic
|
| Line 632... |
Line 626... |
--
|
--
|
-- 25 MHz VGA Pixel clock
|
-- 25 MHz VGA Pixel clock
|
--
|
--
|
vga_clk_buffer : BUFG port map(
|
vga_clk_buffer : BUFG port map(
|
i => clock_div(0),
|
i => clock_div(0),
|
o => pix_clk
|
o => vga_clk
|
);
|
);
|
|
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
--
|
--
|
-- Process to decode memory map
|
-- Process to decode memory map
|
