| Line 130... |
Line 130... |
use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library work;
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library work;
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use work.common.all;
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use work.common.all;
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use WORK.xsasdram.all;
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library unisim;
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library unisim;
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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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|
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entity system09 is
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entity system09 is
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port(
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port(
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CLKA : in Std_Logic; -- 100MHz Clock input
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CLKA : in Std_Logic; -- 100MHz Clock input
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-- CLKB : in Std_Logic; -- 50MHz Clock input
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-- CLKB : in Std_Logic; -- 50MHz Clock input
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SW2_N : in Std_logic; -- Master Reset input (active low)
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SW2_N : in Std_logic; -- Master Reset input (active low)
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SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low)
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SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low)
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|
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-- PS/2 Keyboard
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ps2_clk : inout Std_logic;
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ps2_dat : inout Std_Logic;
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|
|
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-- CRTC output signals
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vga_vsync_n : out Std_Logic;
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vga_hsync_n : out Std_Logic;
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vga_blue : out std_logic_vector(2 downto 0);
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vga_green : out std_logic_vector(2 downto 0);
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vga_red : out std_logic_vector(2 downto 0);
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-- RS232 Port
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-- RS232 Port
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RS232_RXD : in Std_Logic;
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RS232_RXD : in Std_Logic;
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RS232_TXD : out Std_Logic;
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RS232_TXD : out Std_Logic;
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RS232_CTS : in Std_Logic;
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RS232_RTS : out Std_Logic;
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-- Status 7 segment LED
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-- Status 7 segment LED
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S : out std_logic_vector(7 downto 0);
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S : out std_logic_vector(7 downto 0)
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|
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-- SDRAM side
|
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SDRAM_clkfb : in std_logic; -- feedback SDRAM clock after PCB delays
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SDRAM_clkout : out std_logic; -- clock to SDRAM
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SDRAM_CKE : out std_logic; -- clock-enable to SDRAM
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SDRAM_CS_N : out std_logic; -- chip-select to SDRAM
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SDRAM_RAS_N : out std_logic; -- SDRAM row address strobe
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SDRAM_CAS_N : out std_logic; -- SDRAM column address strobe
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SDRAM_WE_N : out std_logic; -- SDRAM write enable
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SDRAM_BA : out std_logic_vector(1 downto 0); -- SDRAM bank address
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SDRAM_A : out std_logic_vector(12 downto 0); -- SDRAM row/column address
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SDRAM_D : inout std_logic_vector(15 downto 0); -- data from SDRAM
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SDRAM_DQMH : out std_logic; -- enable upper-byte of SDRAM databus if true
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SDRAM_DQML : out std_logic; -- enable lower-byte of SDRAM databus if true
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-- Peripheral I/O bus $E100 - $E1FF
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PB_RD_N : out std_logic;
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PB_WR_N : out std_logic;
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PB_A : out std_logic_vector(4 downto 0);
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PB_D : inout std_logic_vector(15 downto 0);
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-- IDE Compact Flash $E100 - $E13F
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ide_dmack_n : out std_logic;
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ide_cs0_n : out std_logic;
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ide_cs1_n : out std_logic;
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-- Ethernet $E140 - $E17F
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ether_cs_n : out std_logic;
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ether_aen : out std_logic; -- Ethernet address enable not
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ether_bhe_n : out std_logic; -- Ethernet bus high enable
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ether_clk : in std_logic; -- Ethernet clock
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ether_rdy : in std_logic; -- Ethernet ready
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ether_irq : in std_logic; -- Ethernet irq - Shared with BAR6
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-- Slot 1 $E180 - $E1BF
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slot1_cs_n : out std_logic;
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-- slot1_irq : in std_logic;
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-- Slot 2 $E1C0 - $E1FF
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slot2_cs_n : out std_logic;
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-- slot2_irq : in std_logic;
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-- CPU Debug Interface signals
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-- CPU Debug Interface signals
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-- cpu_reset_o : out Std_Logic;
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-- cpu_reset_o : out Std_Logic;
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-- cpu_clk_o : out Std_Logic;
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-- cpu_clk_o : out Std_Logic;
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-- cpu_rw_o : out std_logic;
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-- cpu_rw_o : out std_logic;
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| Line 216... |
Line 165... |
-- cpu_nmi_o : out std_logic;
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-- cpu_nmi_o : out std_logic;
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-- cpu_addr_o : out std_logic_vector(15 downto 0);
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-- cpu_addr_o : out std_logic_vector(15 downto 0);
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-- cpu_data_in_o : out std_logic_vector(7 downto 0);
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-- cpu_data_in_o : out std_logic_vector(7 downto 0);
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-- cpu_data_out_o : out std_logic_vector(7 downto 0);
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-- cpu_data_out_o : out std_logic_vector(7 downto 0);
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-- Disable Flash
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FLASH_CE_N : out std_logic
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);
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);
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end system09;
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end system09;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for System09
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-- Architecture for System09
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| Line 369... |
Line 316... |
ram_state_rd1, ram_state_rd2,
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ram_state_rd1, ram_state_rd2,
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ram_state_wr1,
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ram_state_wr1,
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ram_state_3 );
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ram_state_3 );
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signal ram_state : ram_type;
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signal ram_state : ram_type;
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signal flash_ce_n : std_logic;
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signal rs232_cts : Std_Logic;
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signal rs232_rts : Std_Logic;
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signal ether_cs_n : std_logic;
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signal ether_aen : std_logic;
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signal ether_bhe_n : std_logic;
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signal slot1_cs_n : std_logic;
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signal slot2_cs_n : std_logic;
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-- signal BaudCount : std_logic_vector(5 downto 0);
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-- signal BaudCount : std_logic_vector(5 downto 0);
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signal CountL : std_logic_vector(23 downto 0);
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signal CountL : std_logic_vector(23 downto 0);
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signal clk_count : natural range 0 to CPU_CLK_DIV;
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signal clk_count : natural range 0 to CPU_CLK_DIV;
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signal Clk25 : std_logic;
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signal Clk25 : std_logic;
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signal vga_clk : std_logic;
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signal vga_clk : std_logic;
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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--
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--
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-- CPU09 CPU core
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-- CPU09 CPU core
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| Line 399... |
Line 356... |
halt: in std_logic;
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halt: in std_logic;
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hold: in std_logic
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hold: in std_logic
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);
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);
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end component;
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end component;
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----------------------------------------
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----------------------------------------
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--
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--
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-- 4K Block RAM Monitor ROM
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-- 4K Block RAM Monitor ROM
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-- $F000 - $FFFF
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--
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--
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----------------------------------------
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----------------------------------------
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component mon_rom
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component mon_rom
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Port (
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Port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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cs : in std_logic;
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| Line 417... |
Line 375... |
data_out : out std_logic_vector (7 downto 0);
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data_out : out std_logic_vector (7 downto 0);
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data_in : in std_logic_vector (7 downto 0)
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data_in : in std_logic_vector (7 downto 0)
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);
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);
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end component;
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end component;
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----------------------------------------
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----------------------------------------
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--
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--
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-- 8KBytes Block RAM for FLEX9
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-- 8KBytes Block RAM for FLEX9
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-- $C000 - $DFFF
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-- $C000 - $DFFF
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--
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--
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----------------------------------------
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----------------------------------------
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component flex_ram
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component flex_ram
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Port (
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Port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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cs : in std_logic;
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| Line 458... |
Line 416... |
TxC : in Std_Logic; -- Transmit Baud Clock
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TxC : in Std_Logic; -- Transmit Baud Clock
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RxD : in Std_Logic; -- Receive Data
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RxD : in Std_Logic; -- Receive Data
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TxD : out Std_Logic; -- Transmit Data
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TxD : out Std_Logic; -- Transmit Data
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DCD_n : in Std_Logic; -- Data Carrier Detect
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DCD_n : in Std_Logic; -- Data Carrier Detect
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CTS_n : in Std_Logic; -- Clear To Send
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CTS_n : in Std_Logic; -- Clear To Send
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RTS_n : out Std_Logic ); -- Request To send
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RTS_n : out Std_Logic -- Request To send
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);
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end component;
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end component;
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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--
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--
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-- ACIA Clock divider
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-- ACIA Clock divider
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--
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--
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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| Line 480... |
Line 438... |
ACIA_clk : out Std_logic -- ACIA Clock output
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ACIA_clk : out Std_logic -- ACIA Clock output
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);
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);
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end component;
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end component;
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----------------------------------------
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--
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-- PS/2 Keyboard
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--
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----------------------------------------
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component keyboard
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generic(
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KBD_CLK_FREQ : integer := CPU_CLK_FREQ
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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rw : in std_logic;
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addr : in std_logic;
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data_in : in std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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irq : out std_logic;
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kbd_clk : inout std_logic;
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kbd_data : inout std_logic
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);
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end component;
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|
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----------------------------------------
|
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--
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-- Video Display Unit.
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--
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----------------------------------------
|
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component vdu8
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generic(
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VDU_CLK_FREQ : integer := CPU_CLK_FREQ; -- HZ
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VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- HZ
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VGA_HOR_CHARS : integer := 80; -- CHARACTERS
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VGA_VER_CHARS : integer := 25; -- CHARACTERS
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VGA_PIX_PER_CHAR : integer := 8; -- PIXELS
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VGA_LIN_PER_CHAR : integer := 16; -- LINES
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VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
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VGA_HOR_SYNC : integer := 96; -- PIXELS
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VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
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VGA_VER_BACK_PORCH : integer := 13; -- LINES
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VGA_VER_SYNC : integer := 2; -- LINES
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VGA_VER_FRONT_PORCH : integer := 35 -- LINES
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);
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port(
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-- control register interface
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vdu_clk : in std_logic; -- CPU Clock - 25MHz
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vdu_rst : in std_logic;
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vdu_cs : in std_logic;
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vdu_rw : in std_logic;
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vdu_addr : in std_logic_vector(2 downto 0);
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vdu_data_in : in std_logic_vector(7 downto 0);
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vdu_data_out : out std_logic_vector(7 downto 0);
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-- vga port connections
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vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
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vga_red_o : out std_logic;
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vga_green_o : out std_logic;
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vga_blue_o : out std_logic;
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vga_hsync_o : out std_logic;
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vga_vsync_o : out std_logic
|
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);
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end component;
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|
|
|
|
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----------------------------------------
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----------------------------------------
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--
|
--
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-- Timer module
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-- Timer module
|
| Line 584... |
Line 479... |
data_out : out std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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irq : out std_logic
|
irq : out std_logic
|
);
|
);
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end component;
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end component;
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
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--
|
-- Dynamic Address Translation Registers
|
-- Dynamic Address Translation Registers
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
|
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component dat_ram
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component dat_ram
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
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| Line 604... |
Line 499... |
data_out : out std_logic_vector(7 downto 0)
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data_out : out std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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|
|
|
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component XSASDRAMCntl
|
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generic(
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FREQ : natural := MEM_CLK_FREQ;-- operating frequency in KHz
|
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CLK_DIV : real := SYS_CLK_DIV; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
|
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PIPE_EN : boolean := PIPE_EN; -- if true, enable pipelined read operations
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MAX_NOP : natural := MAX_NOP; -- number of NOPs before entering self-refresh
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MULTIPLE_ACTIVE_ROWS : boolean := MULTIPLE_ACTIVE_ROWS; -- if true, allow an active row in each bank
|
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DATA_WIDTH : natural := DATA_WIDTH; -- host & SDRAM data width
|
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NROWS : natural := NROWS; -- number of rows in SDRAM array
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NCOLS : natural := NCOLS; -- number of columns in SDRAM array
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HADDR_WIDTH : natural := HADDR_WIDTH; -- host-side address width
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SADDR_WIDTH : natural := SADDR_WIDTH -- SDRAM-side address width
|
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);
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port(
|
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-- host side
|
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clk : in std_logic; -- master clock
|
|
bufclk : out std_logic; -- buffered master clock
|
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clk1x : out std_logic; -- host clock sync'ed to master clock (and divided if CLK_DIV>1)
|
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clk2x : out std_logic; -- double-speed host clock
|
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lock : out std_logic; -- true when host clock is locked to master clock
|
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rst : in std_logic; -- reset
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rd : in std_logic; -- initiate read operation
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wr : in std_logic; -- initiate write operation
|
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uds : in std_logic; -- upper data strobe
|
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lds : in std_logic; -- lower data strobe
|
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earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async)
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opBegun : out std_logic; -- read/write/self-refresh op begun (clocked)
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rdPending : out std_logic; -- read operation(s) are still in the pipeline
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done : out std_logic; -- read or write operation is done
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rdDone : out std_logic; -- read done and data is available
|
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hAddr : in std_logic_vector(HADDR_WIDTH-1 downto 0); -- address from host
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hDIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from host
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hDOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to host
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status : out std_logic_vector(3 downto 0); -- diagnostic status of the FSM
|
|
|
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-- SDRAM side
|
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sclkfb : in std_logic; -- clock from SDRAM after PCB delays
|
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sclk : out std_logic; -- SDRAM clock sync'ed to master clock
|
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cke : out std_logic; -- clock-enable to SDRAM
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cs_n : out std_logic; -- chip-select to SDRAM
|
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ras_n : out std_logic; -- SDRAM row address strobe
|
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cas_n : out std_logic; -- SDRAM column address strobe
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we_n : out std_logic; -- SDRAM write enable
|
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ba : out std_logic_vector(1 downto 0); -- SDRAM bank address bits
|
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sAddr : out std_logic_vector(SADDR_WIDTH-1 downto 0); -- SDRAM row/column address
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sData : inout std_logic_vector(DATA_WIDTH-1 downto 0); -- SDRAM in/out databus
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dqmh : out std_logic; -- high databits I/O mask
|
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dqml : out std_logic -- low databits I/O mask
|
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);
|
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end component;
|
|
|
|
--
|
--
|
-- Clock buffer
|
-- Clock buffer
|
--
|
--
|
|
|
component BUFG
|
component BUFG
|
Port (
|
Port (
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i: in std_logic;
|
i: in std_logic;
|
o: out std_logic
|
o: out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
begin
|
begin
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Instantiation of internal components
|
-- Instantiation of internal components
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
my_cpu : cpu09 port map (
|
my_cpu : cpu09
|
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
vma => cpu_vma,
|
vma => cpu_vma,
|
addr => cpu_addr(15 downto 0),
|
addr => cpu_addr(15 downto 0),
|
rw => cpu_rw,
|
rw => cpu_rw,
|
| Line 685... |
Line 532... |
nmi => cpu_nmi,
|
nmi => cpu_nmi,
|
halt => cpu_halt,
|
halt => cpu_halt,
|
hold => cpu_hold
|
hold => cpu_hold
|
);
|
);
|
|
|
my_rom : mon_rom port map (
|
my_rom : mon_rom
|
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => rom_cs,
|
cs => rom_cs,
|
rw => '1',
|
rw => '1',
|
addr => cpu_addr(11 downto 0),
|
addr => cpu_addr(11 downto 0),
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => rom_data_out
|
data_out => rom_data_out
|
);
|
);
|
|
|
my_flex : flex_ram port map (
|
my_flex : flex_ram
|
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => flex_cs,
|
cs => flex_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(12 downto 0),
|
addr => cpu_addr(12 downto 0),
|
data_out => flex_data_out,
|
data_out => flex_data_out,
|
data_in => cpu_data_out
|
data_in => cpu_data_out
|
);
|
);
|
|
|
my_acia : acia6850 port map (
|
my_acia : acia6850
|
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => acia_cs,
|
cs => acia_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(0),
|
addr => cpu_addr(0),
|
| Line 723... |
Line 573... |
DCD_n => dcd_n,
|
DCD_n => dcd_n,
|
CTS_n => cts_n,
|
CTS_n => cts_n,
|
RTS_n => rts_n
|
RTS_n => rts_n
|
);
|
);
|
|
|
|
|
my_ACIA_Clock : ACIA_Clock
|
my_ACIA_Clock : ACIA_Clock
|
generic map(
|
generic map(
|
SYS_CLK_FREQ => SYS_CLK_FREQ,
|
SYS_CLK_FREQ => SYS_CLK_FREQ,
|
ACIA_CLK_FREQ => ACIA_CLK_FREQ
|
ACIA_CLK_FREQ => ACIA_CLK_FREQ
|
)
|
)
|
port map(
|
port map(
|
clk => Clk_i,
|
clk => Clk_i,
|
acia_clk => acia_clk
|
acia_clk => acia_clk
|
);
|
);
|
|
|
----------------------------------------
|
|
--
|
|
-- PS/2 Keyboard Interface
|
|
--
|
|
----------------------------------------
|
|
my_keyboard : keyboard
|
|
generic map (
|
|
KBD_CLK_FREQ => CPU_CLK_FREQ
|
|
)
|
|
port map(
|
|
clk => cpu_clk,
|
|
rst => cpu_reset,
|
|
cs => keyboard_cs,
|
|
rw => cpu_rw,
|
|
addr => cpu_addr(0),
|
|
data_in => cpu_data_out(7 downto 0),
|
|
data_out => keyboard_data_out(7 downto 0),
|
|
irq => keyboard_irq,
|
|
kbd_clk => ps2_clk,
|
|
kbd_data => ps2_dat
|
|
);
|
|
|
|
----------------------------------------
|
|
--
|
|
-- Video Display Unit instantiation
|
|
--
|
|
----------------------------------------
|
|
my_vdu : vdu8
|
|
generic map(
|
|
VDU_CLK_FREQ => CPU_CLK_FREQ, -- HZ
|
|
VGA_CLK_FREQ => VGA_CLK_FREQ, -- HZ
|
|
VGA_HOR_CHARS => 80, -- CHARACTERS
|
|
VGA_VER_CHARS => 25, -- CHARACTERS
|
|
VGA_PIX_PER_CHAR => 8, -- PIXELS
|
|
VGA_LIN_PER_CHAR => 16, -- LINES
|
|
VGA_HOR_BACK_PORCH => 40, -- PIXELS
|
|
VGA_HOR_SYNC => 96, -- PIXELS
|
|
VGA_HOR_FRONT_PORCH => 24, -- PIXELS
|
|
VGA_VER_BACK_PORCH => 13, -- LINES
|
|
VGA_VER_SYNC => 2, -- LINES
|
|
VGA_VER_FRONT_PORCH => 35 -- LINES
|
|
)
|
|
port map(
|
|
|
|
-- Control Registers
|
|
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
|
|
vdu_rst => cpu_reset,
|
|
vdu_cs => vdu_cs,
|
|
vdu_rw => cpu_rw,
|
|
vdu_addr => cpu_addr(2 downto 0),
|
|
vdu_data_in => cpu_data_out,
|
|
vdu_data_out => vdu_data_out,
|
|
|
|
-- vga port connections
|
|
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
|
|
vga_red_o => vga_red_o,
|
|
vga_green_o => vga_green_o,
|
|
vga_blue_o => vga_blue_o,
|
|
vga_hsync_o => vga_hsync_n,
|
|
vga_vsync_o => vga_vsync_n
|
|
);
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Timer Module
|
-- Timer Module
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_timer : timer port map (
|
my_timer : timer
|
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => timer_cs,
|
cs => timer_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(0),
|
addr => cpu_addr(0),
|
| Line 817... |
Line 606... |
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Bus Trap Interrupt logic
|
-- Bus Trap Interrupt logic
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_trap : trap port map (
|
my_trap : trap
|
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => trap_cs,
|
cs => trap_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
vma => cpu_vma,
|
vma => cpu_vma,
|
| Line 829... |
Line 619... |
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => trap_data_out,
|
data_out => trap_data_out,
|
irq => trap_irq
|
irq => trap_irq
|
);
|
);
|
|
|
|
my_dat : dat_ram
|
my_dat : dat_ram port map (
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => dat_cs,
|
cs => dat_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr_hi => cpu_addr(15 downto 12),
|
addr_hi => cpu_addr(15 downto 12),
|
addr_lo => cpu_addr(3 downto 0),
|
addr_lo => cpu_addr(3 downto 0),
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => dat_addr(7 downto 0)
|
data_out => dat_addr(7 downto 0)
|
);
|
);
|
|
|
------------------------------------------------------------------------
|
|
-- Instantiate the SDRAM controller that connects to the memory tester
|
|
-- module and interfaces to the external SDRAM chip.
|
|
------------------------------------------------------------------------
|
|
u1 : xsaSDRAMCntl
|
|
generic map(
|
|
FREQ => MEM_CLK_FREQ,
|
|
CLK_DIV => SYS_CLK_DIV,
|
|
PIPE_EN => PIPE_EN,
|
|
MAX_NOP => MAX_NOP,
|
|
MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS,
|
|
DATA_WIDTH => DATA_WIDTH,
|
|
NROWS => NROWS,
|
|
NCOLS => NCOLS,
|
|
HADDR_WIDTH => HADDR_WIDTH,
|
|
SADDR_WIDTH => SADDR_WIDTH
|
|
)
|
|
port map(
|
|
-- Host Side
|
|
clk => CLKA, -- master clock from external clock source (unbuffered)
|
|
bufclk => open, -- buffered master clock output
|
|
clk1x => clk_i, -- synchronized master clock (accounts for delays to external SDRAM)
|
|
clk2x => open, -- synchronized doubled master clock
|
|
lock => lock, -- DLL lock indicator
|
|
rst => rst_i, -- reset
|
|
rd => hRd, -- host-side SDRAM read control from memory tester
|
|
wr => hWr, -- host-side SDRAM write control from memory tester
|
|
uds => hUds, -- host-side SDRAM upper data strobe
|
|
lds => hLds, -- host-side SDRAM lower data strobe
|
|
rdPending => rdPending,-- read operation to SDRAM is in progress
|
|
opBegun => opBegun, -- indicates memory read/write has begun
|
|
earlyOpBegun => earlyBegun, -- early indicator that memory operation has begun
|
|
rdDone => rdDone, -- indicates SDRAM memory read operation is done
|
|
done => ramDone, -- indicates SDRAM memory read or write operation is done
|
|
hAddr => hAddr, -- host-side address from memory tester to SDRAM
|
|
hDIn => hDIn, -- test data pattern from memory tester to SDRAM
|
|
hDOut => hDOut, -- SDRAM data output to memory tester
|
|
status => open, -- SDRAM controller state (for diagnostics)
|
|
-- SDRAM Side
|
|
sclkfb => SDRAM_clkfb, -- clock feedback with added external PCB delays
|
|
sclk => SDRAM_clkout, -- synchronized clock to external SDRAM
|
|
cke => SDRAM_cke, -- SDRAM clock enable
|
|
cs_n => SDRAM_cs_n, -- SDRAM chip-select
|
|
ras_n => SDRAM_ras_n, -- SDRAM RAS
|
|
cas_n => SDRAM_cas_n, -- SDRAM CAS
|
|
we_n => SDRAM_we_n, -- SDRAM write-enable
|
|
ba => SDRAM_ba, -- SDRAM bank address
|
|
sAddr => SDRAM_A, -- SDRAM address
|
|
sData => SDRAM_D, -- SDRAM databus
|
|
dqmh => SDRAM_dqmh, -- SDRAM DQMH
|
|
dqml => SDRAM_dqml -- SDRAM DQML
|
|
);
|
|
|
|
cpu_clk_buffer : BUFG port map(
|
cpu_clk_buffer : BUFG
|
|
port map(
|
i => Clk25,
|
i => Clk25,
|
o => cpu_clk
|
o => cpu_clk
|
);
|
);
|
|
|
vga_clk_buffer : BUFG port map(
|
|
i => Clk25,
|
|
o => vga_clk
|
|
);
|
|
|
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
--
|
--
|
-- Process to decode memory map
|
-- Process to decode memory map
|
--
|
--
|
| Line 938... |
Line 673... |
ide_cs <= '0';
|
ide_cs <= '0';
|
ether_cs <= '0';
|
ether_cs <= '0';
|
slot1_cs <= '0';
|
slot1_cs <= '0';
|
slot2_cs <= '0';
|
slot2_cs <= '0';
|
ram_cs <= '0';
|
ram_cs <= '0';
|
if cpu_addr( 15 downto 8 ) = "11111111" then
|
|
|
if cpu_addr( 15 downto 8 ) = "11111111" then -- $FFxx
|
cpu_data_in <= rom_data_out;
|
cpu_data_in <= rom_data_out;
|
dat_cs <= cpu_vma; -- write DAT
|
dat_cs <= cpu_vma; -- write DAT
|
rom_cs <= cpu_vma; -- read ROM
|
rom_cs <= cpu_vma; -- read ROM
|
|
|
--
|
--
|
-- Sys09Bug Monitor ROM $F000 - $FFFF
|
-- Sys09Bug Monitor ROM $F000 - $FFFF
|
--
|
--
|
elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
|
elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
|
cpu_data_in <= rom_data_out;
|
cpu_data_in <= rom_data_out;
|
| Line 1019... |
Line 756... |
-- Remaining 6 slots reserved for non SWTPc Peripherals
|
-- Remaining 6 slots reserved for non SWTPc Peripherals
|
--
|
--
|
when others => -- $E0A0 to $E0FF
|
when others => -- $E0A0 to $E0FF
|
null;
|
null;
|
end case;
|
end case;
|
|
|
--
|
--
|
-- XST-3.0 Peripheral Bus goes here
|
-- XST-3.0 Peripheral Bus goes here
|
-- $E100 to $E1FF
|
-- $E100 to $E1FF
|
-- Four devices
|
-- Four devices
|
-- IDE, Ethernet, Slot1, Slot2
|
-- IDE, Ethernet, Slot1, Slot2
|
| Line 1055... |
Line 793... |
-- Nothing else
|
-- Nothing else
|
--
|
--
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
|
|
--
|
--
|
-- $E200 to $EFFF reserved for future use
|
-- $E200 to $EFFF reserved for future use
|
--
|
--
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
|
|
--
|
--
|
-- Flex RAM $0C000 - $0DFFF
|
-- Flex RAM $0C000 - $0DFFF
|
--
|
--
|
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
|
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
|
cpu_data_in <= flex_data_out;
|
cpu_data_in <= flex_data_out;
|
flex_cs <= cpu_vma;
|
flex_cs <= cpu_vma;
|
|
|
--
|
--
|
-- Everything else is RAM
|
-- Everything else is RAM
|
--
|
--
|
else
|
else
|
cpu_data_in <= ram_data_out;
|
cpu_data_in <= ram_data_out;
|
ram_cs <= cpu_vma;
|
ram_cs <= cpu_vma;
|
end if;
|
end if;
|
end process;
|
|
|
|
|
|
--
|
|
-- 16-bit Peripheral Bus
|
|
-- 6809 Big endian
|
|
-- ISA bus little endian
|
|
-- Not sure about IDE interface
|
|
--
|
|
peripheral_bus: process( clk_i, cpu_reset, cpu_rw, cpu_addr, cpu_data_out,
|
|
pb_cs, pb_wreg, pb_rreg )
|
|
begin
|
|
pb_wru <= pb_cs and (not cpu_rw) and (not cpu_addr(0));
|
|
pb_wrl <= pb_cs and (not cpu_rw) and cpu_addr(0) ;
|
|
pb_rdu <= pb_cs and cpu_rw and (not cpu_addr(0));
|
|
pb_rdl <= pb_cs and cpu_rw and cpu_addr(0) ;
|
|
pb_a <= cpu_addr(5 downto 1);
|
|
|
|
--
|
|
-- Register upper byte from CPU on first CPU write
|
|
-- and lower byte from the peripheral bus on first CPU read
|
|
--
|
|
if cpu_reset = '1' then
|
|
pb_wreg <= (others => '0');
|
|
pb_rreg <= (others => '0');
|
|
elsif clk_i'event and clk_i ='1' then
|
|
if pb_wru = '1' then
|
|
pb_wreg <= cpu_data_out;
|
|
end if;
|
|
if pb_rdu = '1' then
|
|
pb_rreg <= pb_d(7 downto 0);
|
|
end if;
|
|
end if;
|
|
--
|
|
-- Peripheral bus read and write strobes are
|
|
-- Syncronized with the 50 MHz clock
|
|
-- and are asserted until the peripheral bus hold is released
|
|
--
|
|
if cpu_reset = '1' then
|
|
pb_wr_n <= '1';
|
|
pb_rd_n <= '1';
|
|
elsif clk_i'event and clk_i ='1' then
|
|
if pb_hold = '1' then
|
|
pb_wr_n <= not pb_wrl;
|
|
pb_rd_n <= not pb_rdu;
|
|
else
|
|
pb_wr_n <= '1';
|
|
pb_rd_n <= '1';
|
|
end if;
|
|
end if;
|
|
--
|
|
-- The peripheral bus will be an output
|
|
-- the registered even byte on data(15 downto 8)
|
|
-- and the CPU odd bytes on data(7 downto 0)
|
|
-- on odd byte writes
|
|
--
|
|
if pb_wrl = '1' then
|
|
pb_d <= pb_wreg & cpu_data_out;
|
|
else
|
|
pb_d <= (others => 'Z');
|
|
end if;
|
|
|
|
--
|
|
-- On even byte reads,
|
|
-- the CPU reads the low (even) byte of the peripheral bus
|
|
-- On odd byte reads,
|
|
-- the CPU reads the registered (odd byte) input from the peripheral bus
|
|
--
|
|
if pb_rdu = '1' then
|
|
pb_data_out <= pb_d(15 downto 8);
|
|
elsif pb_rdl = '1' then
|
|
pb_data_out <= pb_rreg;
|
|
else
|
|
pb_data_out <= (others => '0');
|
|
end if;
|
|
|
|
end process;
|
end process;
|
|
|
--
|
|
-- Hold Peripheral bus accesses for a few cycles
|
|
--
|
|
peripheral_bus_hold: process( cpu_clk, cpu_reset, pb_rdu, pb_wrl ) --, ether_rdy )
|
|
begin
|
|
if cpu_reset = '1' then
|
|
pb_release <= '0';
|
|
pb_count <= "0000";
|
|
pb_hold_state <= hold_release_state;
|
|
elsif rising_edge(cpu_clk) then
|
|
--
|
|
-- The perpheral bus hold signal should be generated on
|
|
-- 16 bit bus read which will be on even byte reads or
|
|
-- 16 bit bus write which will be on odd byte writes.
|
|
--
|
|
case pb_hold_state is
|
|
when hold_release_state =>
|
|
pb_release <= '0';
|
|
if (pb_rdu = '1') or (pb_wrl = '1') then
|
|
pb_count <= "0100";
|
|
pb_hold_state <= hold_request_state;
|
|
elsif (pb_rdl = '1') or (pb_wru = '1') then
|
|
pb_release <= '1';
|
|
pb_hold_state <= hold_release_state;
|
|
end if;
|
|
|
|
when hold_request_state =>
|
|
if pb_count = "0000" then
|
|
-- if ether_rdy = '1' then
|
|
pb_release <= '1';
|
|
pb_hold_state <= hold_release_state;
|
|
-- end if;
|
|
else
|
|
pb_count <= pb_count - "0001";
|
|
end if;
|
|
when others =>
|
|
null;
|
|
end case;
|
|
end if;
|
|
end process;
|
|
|
|
--
|
|
-- Compact Flash Control
|
|
--
|
|
compact_flash: process( ide_cs, cpu_addr )
|
|
begin
|
|
ide_cs0_n <= not( ide_cs ) or cpu_addr(4);
|
|
ide_cs1_n <= not( ide_cs and cpu_addr(4));
|
|
ide_dmack_n <= '1';
|
|
end process;
|
|
|
|
--
|
--
|
-- Interrupts and other bus control signals
|
-- Interrupts and other bus control signals
|
--
|
--
|
interrupts : process( SW3_N,
|
interrupts : process( SW3_N,
|
| Line 1224... |
Line 841... |
cpu_halt <= '0';
|
cpu_halt <= '0';
|
cpu_hold <= pb_hold or ram_hold;
|
cpu_hold <= pb_hold or ram_hold;
|
FLASH_CE_N <= '1';
|
FLASH_CE_N <= '1';
|
end process;
|
end process;
|
|
|
|
|
--
|
--
|
-- Flash 7 segment LEDS
|
-- Flash 7 segment LEDS
|
--
|
--
|
my_led_flasher: process( clk_i, rst_i, CountL )
|
my_led_flasher: process( clk_i, rst_i, CountL )
|
begin
|
begin
|
| Line 1244... |
Line 860... |
-- Generate CPU & Pixel Clock from Memory Clock
|
-- Generate CPU & Pixel Clock from Memory Clock
|
--
|
--
|
my_prescaler : process( clk_i, clk_count )
|
my_prescaler : process( clk_i, clk_count )
|
begin
|
begin
|
if rising_edge( clk_i ) then
|
if rising_edge( clk_i ) then
|
|
|
if clk_count = 0 then
|
if clk_count = 0 then
|
clk_count <= CPU_CLK_DIV-1;
|
clk_count <= CPU_CLK_DIV-1;
|
else
|
else
|
clk_count <= clk_count - 1;
|
clk_count <= clk_count - 1;
|
end if;
|
end if;
|
|
|
if clk_count = 0 then
|
if clk_count = 0 then
|
clk25 <= '0';
|
clk25 <= '0';
|
elsif clk_count = (CPU_CLK_DIV/2) then
|
elsif clk_count = (CPU_CLK_DIV/2) then
|
clk25 <= '1';
|
clk25 <= '1';
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--
|
--
|
-- Reset button and reset timer
|
-- Reset button and reset timer
|
| Line 1300... |
Line 913... |
begin
|
begin
|
slot1_cs_n <= not slot1_cs;
|
slot1_cs_n <= not slot1_cs;
|
slot2_cs_n <= not slot2_cs;
|
slot2_cs_n <= not slot2_cs;
|
end process;
|
end process;
|
|
|
--
|
|
-- VGA ouputs
|
|
--
|
|
my_vga_assignments : process( vga_red_o, vga_green_o, vga_blue_o )
|
|
begin
|
|
VGA_red(0) <= vga_red_o;
|
|
VGA_red(1) <= vga_red_o;
|
|
VGA_red(2) <= vga_red_o;
|
|
VGA_green(0) <= vga_green_o;
|
|
VGA_green(1) <= vga_green_o;
|
|
VGA_green(2) <= vga_green_o;
|
|
VGA_blue(0) <= vga_blue_o;
|
|
VGA_blue(1) <= vga_blue_o;
|
|
VGA_blue(2) <= vga_blue_o;
|
|
end process;
|
|
|
|
--
|
|
-- SDRAM read write control
|
|
--
|
|
my_sdram_rw : process( clk_i, cpu_reset,
|
|
opBegun, ramDone,
|
|
ram_state,
|
|
ram_rd_req, ram_wr_req )
|
|
begin
|
|
if( cpu_reset = '1' ) then
|
|
hRd <= '0';
|
|
hWr <= '0';
|
|
ram_hold <= '0';
|
|
ram_state <= ram_state_0;
|
|
|
|
elsif( falling_edge(clk_i) ) then
|
|
--
|
|
-- ram state machine
|
|
--
|
|
case ram_state is
|
|
|
|
when ram_state_0 =>
|
|
if ram_rd_req = '1' then
|
|
ram_hold <= '1';
|
|
hRd <= '1';
|
|
ram_state <= ram_state_rd1;
|
|
elsif ram_wr_req = '1' then
|
|
ram_hold <= '1';
|
|
hWr <= '1';
|
|
ram_state <= ram_state_wr1;
|
|
end if;
|
|
|
|
when ram_state_rd1 =>
|
|
if opBegun = '1' then
|
|
hRd <= '0';
|
|
ram_state <= ram_state_rd2;
|
|
end if;
|
|
|
|
when ram_state_rd2 =>
|
|
if ramDone = '1' then
|
|
ram_hold <= '0';
|
|
ram_state <= ram_state_3;
|
|
end if;
|
|
|
|
when ram_state_wr1 =>
|
|
if opBegun = '1' then
|
|
ram_hold <= '0';
|
|
hWr <= '0';
|
|
ram_state <= ram_state_3;
|
|
end if;
|
|
|
|
when ram_state_3 =>
|
|
if ram_release = '1' then
|
|
ram_state <= ram_state_0;
|
|
end if;
|
|
|
|
when others =>
|
|
hRd <= '0';
|
|
hWr <= '0';
|
|
ram_hold <= '0';
|
|
ram_state <= ram_state_0;
|
|
end case;
|
|
|
|
end if;
|
|
end process;
|
|
|
|
--
|
|
-- SDRAM Address and data bus assignments
|
|
--
|
|
my_sdram_addr_data : process( cpu_addr, dat_addr,
|
|
cpu_data_out, hDout )
|
|
begin
|
|
hAddr(23 downto 19) <= "00000";
|
|
hAddr(18 downto 11) <= dat_addr;
|
|
hAddr(10 downto 0) <= cpu_addr(11 downto 1);
|
|
hUds <= not cpu_addr(0);
|
|
hLds <= cpu_addr(0);
|
|
if cpu_addr(0) = '0' then
|
|
hDin( 7 downto 0) <= (others=>'0');
|
|
hDin(15 downto 8) <= cpu_data_out;
|
|
ram_data_out <= hDout(15 downto 8);
|
|
else
|
|
hDin( 7 downto 0) <= cpu_data_out;
|
|
hDin(15 downto 8) <= (others=>'0');
|
|
ram_data_out <= hDout( 7 downto 0);
|
|
end if;
|
|
end process;
|
|
|
|
--
|
|
-- Hold RAM until falling CPU clock edge
|
|
--
|
|
ram_bus_hold: process( cpu_clk, cpu_reset, ram_hold )
|
|
begin
|
|
if ram_hold = '1' then
|
|
ram_release <= '0';
|
|
elsif falling_edge(cpu_clk) then
|
|
ram_release <= '1';
|
|
end if;
|
|
end process;
|
|
|
|
--
|
--
|
-- CPU read data request on rising CPU clock edge
|
-- CPU read data request on rising CPU clock edge
|
--
|
--
|
ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release )
|
ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release )
|
| Line 1443... |
Line 942... |
ram_wr_req <= '1';
|
ram_wr_req <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
|
|
status_leds : process( rst_i, cpu_reset, lock )
|
status_leds : process( rst_i, cpu_reset, lock )
|
begin
|
begin
|
S(0) <= rst_i;
|
S(0) <= rst_i;
|
S(1) <= cpu_reset;
|
S(1) <= cpu_reset;
|
S(2) <= lock;
|
S(2) <= lock;
|
| Line 1473... |
Line 970... |
-- cpu_addr_o <= cpu_addr;
|
-- cpu_addr_o <= cpu_addr;
|
-- cpu_data_out_o <= cpu_data_out;
|
-- cpu_data_out_o <= cpu_data_out;
|
-- cpu_data_in_o <= cpu_data_in;
|
-- cpu_data_in_o <= cpu_data_in;
|
--end process;
|
--end process;
|
|
|
|
|
end rtl; --===================== End of architecture =======================--
|
end rtl; --===================== End of architecture =======================--
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
