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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Diff between revs 170 and 173

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Rev 170 Rev 173
Line 200... Line 200...
  signal DCD_n          : Std_Logic;
  signal DCD_n          : Std_Logic;
  signal RTS_n          : Std_Logic;
  signal RTS_n          : Std_Logic;
  signal CTS_n          : Std_Logic;
  signal CTS_n          : Std_Logic;
 
 
  -- RAM
  -- RAM
  signal ram_cs         : std_logic;
  signal ram1_cs         : std_logic;
  signal ram_data_out   : std_logic_vector(7 downto 0);
  signal ram1_data_out   : std_logic_vector(7 downto 0);
 
  signal ram2_cs         : std_logic;
 
  signal ram2_data_out   : std_logic_vector(7 downto 0);
 
  signal ram3_cs         : std_logic;
 
 
  -- CPU Interface signals
  -- CPU Interface signals
  signal cpu_reset      : Std_Logic;
  signal cpu_reset      : Std_Logic;
  signal cpu_clk        : Std_Logic;
  signal cpu_clk        : Std_Logic;
  signal cpu_rw         : std_logic;
  signal cpu_rw         : std_logic;
Line 322... Line 325...
    data_in    : in  std_logic_vector (7 downto 0)
    data_in    : in  std_logic_vector (7 downto 0)
  );
  );
end component;
end component;
 
 
 
 
 
----------------------------------------
 
--
 
-- 16KBytes Block RAM 8000
 
-- $8000 - $BFFF
 
--
 
----------------------------------------
 
 
 
component ram_16k
 
  Port (
 
    clk      : in  std_logic;
 
    rst      : in  std_logic;
 
    cs       : in  std_logic;
 
    rw       : in  std_logic;
 
    addr     : in  std_logic_vector (13 downto 0);
 
    data_out    : out std_logic_vector (7 downto 0);
 
    data_in    : in  std_logic_vector (7 downto 0)
 
  );
 
end component;
 
 
-----------------------------------------------------------------
-----------------------------------------------------------------
--
--
-- 6850 Compatible ACIA / UART
-- 6850 Compatible ACIA / UART
--
--
-----------------------------------------------------------------
-----------------------------------------------------------------
Line 484... Line 506...
 
 
  my_32k : ram_32k
  my_32k : ram_32k
    port map (
    port map (
      clk       => cpu_clk,
      clk       => cpu_clk,
      rst       => cpu_reset,
      rst       => cpu_reset,
      cs        => ram_cs,
      cs        => ram1_cs,
      rw        => cpu_rw,
      rw        => cpu_rw,
      addr      => cpu_addr(14 downto 0),
      addr      => cpu_addr(14 downto 0),
      data_out     => ram_data_out,
      data_out     => ram1_data_out,
 
      data_in     => cpu_data_out
 
    );
 
 
 
  my_16k : ram_16k
 
    port map (
 
      clk       => cpu_clk,
 
      rst       => cpu_reset,
 
      cs        => ram2_cs,
 
      rw        => cpu_rw,
 
      addr      => cpu_addr(13 downto 0),
 
      data_out     => ram2_data_out,
      data_in     => cpu_data_out
      data_in     => cpu_data_out
    );
    );
 
 
  my_acia  : acia6850
  my_acia  : acia6850
    port map (
    port map (
Line 586... Line 619...
                     rom_data_out,
                     rom_data_out,
                     flex_data_out,
                     flex_data_out,
                     acia_data_out,
                     acia_data_out,
                     timer_data_out,
                     timer_data_out,
                     trap_data_out,
                     trap_data_out,
                     ram_data_out
                     ram1_data_out, ram2_data_out
                     )
                     )
  begin
  begin
    cpu_data_in <= (others=>'0');
    cpu_data_in <= (others=>'0');
    dat_cs      <= '0';
    dat_cs      <= '0';
    rom_cs      <= '0';
    rom_cs      <= '0';
    flex_cs     <= '0';
    flex_cs     <= '0';
    acia_cs     <= '0';
    acia_cs     <= '0';
    timer_cs    <= '0';
    timer_cs    <= '0';
    trap_cs     <= '0';
    trap_cs     <= '0';
    ram_cs      <= '0';
    ram1_cs      <= '0';
 
    ram2_cs      <= '0';
 
 
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
      cpu_data_in <= rom_data_out;
      cpu_data_in <= rom_data_out;
      dat_cs      <= cpu_vma;              -- write DAT
      dat_cs      <= cpu_vma;              -- write DAT
      rom_cs      <= cpu_vma;              -- read  ROM
      rom_cs      <= cpu_vma;              -- read  ROM
Line 685... Line 719...
 
 
    --
    --
    -- 32k RAM $00000 - $07FFF
    -- 32k RAM $00000 - $07FFF
    --
    --
    elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF
    elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF
      cpu_data_in <= ram_data_out;
      cpu_data_in <= ram1_data_out;
      ram_cs     <= cpu_vma;
      ram1_cs     <= cpu_vma;
 
 
 
    --
 
    -- 16k RAM $08000 - $0BFFF
 
    --
 
    elsif dat_addr(7 downto 1) = "0000100" then -- $08000 - $0BFFF
 
      cpu_data_in <= ram2_data_out;
 
      ram2_cs     <= cpu_vma;
 
 
    --
    --
    -- Everything else is RAM
    -- Everything else is RAM
    --
    --
    else
    else
      cpu_data_in <= ram_data_out;
      cpu_data_in <= (others => '0');
      ram_cs      <= cpu_vma;
      ram3_cs      <= cpu_vma;
    end if;
    end if;
 
 
  end process;
  end process;
 
 
  --
  --

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