OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Diff between revs 173 and 174

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 173 Rev 174
Line 127... Line 127...
   use unisim.vcomponents.all;
   use unisim.vcomponents.all;
 
 
entity system09 is
entity system09 is
  port(
  port(
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
    SW2_N        : in  Std_logic;  -- Master Reset input (active low)
    --SW2_N        : in  Std_logic;  -- Master Reset input (active low)
    SW3_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
    --SW3_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
 
 
    -- RS232 Port
    -- RS232 Port
    RS232_RXD    : in  Std_Logic;
    RS232_RXD    : in  Std_Logic;
    RS232_TXD    : out Std_Logic;
    RS232_TXD    : out Std_Logic;
 
 
    -- Status 7 segment LED
    -- Status 7 segment LED
 
         sw           : in std_logic_vector(7 downto 0);
 
         btn          : in std_logic_vector(4 downto 0);
    S            : out std_logic_vector(7 downto 0)
    S            : out std_logic_vector(7 downto 0)
 
 
 
 
-- CPU Debug Interface signals
-- CPU Debug Interface signals
--    cpu_reset_o     : out Std_Logic;
--    cpu_reset_o     : out Std_Logic;
--    cpu_clk_o       : out Std_Logic;
--    cpu_clk_o       : out Std_Logic;
--    cpu_rw_o        : out std_logic;
--    cpu_rw_o        : out std_logic;
--    cpu_vma_o       : out std_logic;
--    cpu_vma_o       : out std_logic;
Line 167... Line 170...
 
 
  constant MEM_CLK_FREQ         : natural := 100_000; -- operating frequency of Memory in KHz
  constant MEM_CLK_FREQ         : natural := 100_000; -- operating frequency of Memory in KHz
  constant SYS_CLK_DIV          : real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
  constant SYS_CLK_DIV          : real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
 
 
  constant SYS_CLK_FREQ         : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000;  -- FPGA System Clock (in Hz)
  constant SYS_CLK_FREQ         : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000;  -- FPGA System Clock (in Hz)
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
  constant CPU_CLK_FREQ         : natural := 1; --25_000_000;  -- CPU Clock (Hz)
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
 
 
  constant TRESET               : natural := 300;      -- min initialization interval (us)
  constant TRESET               : natural := 300;      -- min initialization interval (us)
  constant RST_CYCLES           : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000));  -- SDRAM power-on initialization interval
  constant RST_CYCLES           : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000));  -- SDRAM power-on initialization interval
 
 
  type hold_state_type is ( hold_release_state, hold_request_state );
 
 
 
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Signals
  -- Signals
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
 
  signal pbtn           : std_logic_vector(4 downto 0);
 
  signal SW3_N : std_logic;
 
  signal SW2_N : std_logic;
  -- BOOT ROM
  -- BOOT ROM
  signal rom_cs         : Std_logic;
  signal rom_cs         : Std_logic;
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
 
 
  -- Flex Memory & Monitor Stack
  -- Flex Memory & Monitor Stack
Line 244... Line 248...
 
 
  signal CountL        : std_logic_vector(23 downto 0);
  signal CountL        : std_logic_vector(23 downto 0);
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
  signal Clk25         : std_logic;
  signal Clk25         : std_logic;
 
 
 
 
 
component btn_debounce
 
    Port ( BTN_I : in  STD_LOGIC_VECTOR (4 downto 0);
 
           CLK : in  STD_LOGIC;
 
           BTN_O : out  STD_LOGIC_VECTOR (4 downto 0));
 
end component;
 
 
 
 
-----------------------------------------------------------------
-----------------------------------------------------------------
--
--
-- CPU09 CPU core
-- CPU09 CPU core
--
--
-----------------------------------------------------------------
-----------------------------------------------------------------
Line 459... Line 471...
  );
  );
end component;
end component;
 
 
begin
begin
 
 
 
 
 
 
 
 
 
 
  clk_i <= CLKA;
  clk_i <= CLKA;
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Instantiation of internal components
  -- Instantiation of internal components
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
 
 
Line 771... Line 787...
  end process;
  end process;
 
 
  --
  --
  -- Generate CPU & Pixel Clock from Memory Clock
  -- Generate CPU & Pixel Clock from Memory Clock
  --
  --
  my_prescaler : process( clk_i, clk_count )
--  my_prescaler : process( clk_i, clk_count )
  begin
--  begin
    if rising_edge( clk_i ) then
--    if rising_edge( clk_i ) then
      if clk_count = 0 then
--      if clk_count = 0 then
        clk_count <= CPU_CLK_DIV-1;
--        clk_count <= CPU_CLK_DIV-1;
      else
--      else
        clk_count <= clk_count - 1;
--        clk_count <= clk_count - 1;
      end if;
--      end if;
      if clk_count = 0 then
--      if clk_count = 0 then
         clk25 <= '0';
--         clk25 <= '0';
      elsif clk_count = (CPU_CLK_DIV/2) then
--      elsif clk_count = (CPU_CLK_DIV/2) then
         clk25 <= '1';
--         clk25 <= '1';
      end if;
--      end if;
    end if;
--    end if;
  end process;
--  end process;
 
 
 
 
 
  my_singlestep: btn_debounce
 
    port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
 
  SW2_N <= pbtn(0);
 
  SW3_N <= pbtn(1);
 
  clk25 <= pbtn(2);
 
 
  --
  --
  -- Reset button and reset timer
  -- Reset button and reset timer
  --
  --
  my_switch_assignments : process( rst_i, SW2_N)
  my_switch_assignments : process( rst_i, SW2_N)
Line 808... Line 831...
    dcd_n     <= '0';
    dcd_n     <= '0';
    RS232_TXD <= txd;
    RS232_TXD <= txd;
    RS232_RTS <= rts_n;
    RS232_RTS <= rts_n;
  end process;
  end process;
 
 
  status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw)
  status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw, sw)
  begin
  begin
    S(0) <= cpu_addr(0);
 
    S(1) <= cpu_addr(1);
 
    S(2) <= cpu_addr(2);
 
    S(3) <= cpu_addr(3);
 
         S(4) <= cpu_addr(4);
 
         S(5) <= cpu_addr(5);
 
         S(6) <= cpu_rw;
 
         S(7) <= '0';
         S(7) <= '0';
    --S(7 downto 4) <= "0000";
    S(6) <= cpu_rw;
 
         S(5) <= cpu_vma;
 
         S(4) <= '0';
 
    case sw is
 
         when "00000000" =>
 
           S(3 downto 0) <= cpu_addr(3 downto 0);
 
    when "00000001" =>
 
           S(3 downto 0) <= cpu_addr(7 downto 4);
 
         when "00000010" =>
 
           S(3 downto 0) <= cpu_addr(11 downto 8);
 
    when "00000011" =>
 
           S(3 downto 0) <= cpu_addr(15 downto 12);
 
    when "00000100" =>
 
           S(3 downto 0) <= cpu_data_in(3 downto 0);
 
    when "00000101" =>
 
           S(3 downto 0) <= cpu_data_in(7 downto 4);
 
    when others => S(3 downto 0) <= (others => '0');
 
         end case;
  end process;
  end process;
 
 
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
--                      cpu_halt, cpu_hold,
--                      cpu_halt, cpu_hold,
--                      cpu_firq, cpu_irq, cpu_nmi,
--                      cpu_firq, cpu_irq, cpu_nmi,

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.