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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Diff between revs 192 and 194

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Rev 192 Rev 194
Line 235... Line 235...
  signal trap_irq       : std_logic;
  signal trap_irq       : std_logic;
 
 
  signal rst_i         : std_logic;     -- internal reset signal
  signal rst_i         : std_logic;     -- internal reset signal
  signal clk_i         : std_logic;     -- internal master clock signal
  signal clk_i         : std_logic;     -- internal master clock signal
 
 
  signal CountL        : std_logic_vector(23 downto 0);
  signal CountL        : std_logic_vector(24 downto 0);
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
  signal Clk25         : std_logic;
  signal Clk25         : std_logic;
 
 
-----------------------------------------------------------------
-----------------------------------------------------------------
--
--
Line 478... Line 478...
  --
  --
  -- Reset button and reset timer
  -- Reset button and reset timer
  --
  --
  my_switch_assignments : process( rst_i, RESET)
  my_switch_assignments : process( rst_i, RESET)
  begin
  begin
    rst_i <= RESET;
    rst_i <= not RESET;
    cpu_reset <= rst_i;
    cpu_reset <= rst_i;
  end process;
  end process;
 
 
  clk_i <= CLKA;
  clk_i <= CLKA;
 
 
Line 576... Line 576...
  begin
  begin
    RXD       <= RS232_RXD;
    RXD       <= RS232_RXD;
    CTS_n     <= RS232_CTS;
    CTS_n     <= RS232_CTS;
    DCD_n     <= '0';
    DCD_n     <= '0';
    RS232_TXD <= TXD;
    RS232_TXD <= TXD;
    RS232_RTS <= RTS_n;
    RS232_RTS <= not RTS_n;
  end process;
  end process;
 
 
  my_ACIA_Clock : ACIA_Clock
  my_ACIA_Clock : ACIA_Clock
    generic map(
    generic map(
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
Line 798... Line 798...
  -- Flash 7 segment LEDS
  -- Flash 7 segment LEDS
  --
  --
  my_led_flasher: process( clk_i, rst_i, CountL )
  my_led_flasher: process( clk_i, rst_i, CountL )
  begin
  begin
    if rst_i = '1' then
    if rst_i = '1' then
         CountL <= "000000000000000000000000";
         CountL <= "0000000000000000000000000";
    elsif rising_edge(clk_i) then
    elsif rising_edge(clk_i) then
         CountL <= CountL + 1;
         CountL <= CountL + 1;
    end if;
    end if;
  end process;
  end process;
 
 
  status_leds : process( rst_i, cpu_reset, cpu_addr, NMI, cpu_data_in, cpu_rw, CountL, sw)
  status_leds : process( rst_i, cpu_reset, cpu_addr, NMI, cpu_data_in, cpu_rw, CountL, sw)
  begin
  begin
    S(7) <= '0';
    S(7) <= '0';
    S(6) <= CountL(23);
    S(6) <= CountL(24);
         S(5) <= cpu_rw;
         S(5) <= cpu_reset;
         S(4) <= NMI;
         S(4) <= NMI;
    case sw is
    case sw is
         when "000" =>
         when "000" =>
           S(3 downto 0) <= cpu_addr(3 downto 0);
           S(3 downto 0) <= cpu_addr(3 downto 0);
    when "001" =>
    when "001" =>

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