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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Diff between revs 194 and 195

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Rev 194 Rev 195
Line 131... Line 131...
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
    RESET        : in  Std_logic;  -- Master Reset input (active high) -- red "RESET" PB
    RESET        : in  Std_logic;  -- Master Reset input (active high) -- red "RESET" PB
    NMI          : in  Std_logic;  -- Non Maskable Interrupt input (active high) -- Center PB
    NMI          : in  Std_logic;  -- Non Maskable Interrupt input (active high) -- Center PB
 
 
    -- RS232 Port - via Pmod RS232
    -- RS232 Port - via Pmod RS232
    RS232_CTS    : in  Std_Logic;
--  RS232_CTS    : in  Std_Logic;
    RS232_RTS    : out Std_Logic;
--  RS232_RTS    : out Std_Logic;
    RS232_RXD    : in  Std_Logic;
    RS232_RXD    : in  Std_Logic;
    RS232_TXD    : out Std_Logic;
    RS232_TXD    : out Std_Logic;
 
 
    -- slide switches
    -- slide switches
         sw           : in std_logic_vector(2 downto 0);
         sw           : in std_logic_vector(2 downto 0);
Line 570... Line 570...
    );
    );
 
 
  --
  --
  -- RS232 signals:
  -- RS232 signals:
  --
  --
  my_acia_assignments : process( RS232_RXD, RS232_CTS, TXD, RTS_n )
  my_acia_assignments : process( RS232_RXD, -- RS232_CTS,
 
                                 TXD, RTS_n )
  begin
  begin
    RXD       <= RS232_RXD;
    RXD       <= RS232_RXD;
    CTS_n     <= RS232_CTS;
    CTS_n     <= '0'; -- RS232_CTS;
    DCD_n     <= '0';
    DCD_n     <= '0';
    RS232_TXD <= TXD;
    RS232_TXD <= TXD;
    RS232_RTS <= not RTS_n;
--  RS232_RTS <= not RTS_n;
  end process;
  end process;
 
 
  my_ACIA_Clock : ACIA_Clock
  my_ACIA_Clock : ACIA_Clock
    generic map(
    generic map(
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,

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