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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Diff between revs 195 and 209

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Rev 195 Rev 209
Line 130... Line 130...
  port(
  port(
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
    RESET        : in  Std_logic;  -- Master Reset input (active high) -- red "RESET" PB
    RESET        : in  Std_logic;  -- Master Reset input (active high) -- red "RESET" PB
    NMI          : in  Std_logic;  -- Non Maskable Interrupt input (active high) -- Center PB
    NMI          : in  Std_logic;  -- Non Maskable Interrupt input (active high) -- Center PB
 
 
 
    -- PS/2 Keyboard
 
    ps2_clk      : inout Std_logic;
 
    ps2_dat      : inout Std_Logic;
 
 
 
    -- VGA port output
 
--  VGA_red      : out std_logic_vector(3 downto 0);
 
    VGA_green    : out std_logic_vector(3 downto 0);
 
--  VGA_blue     : out std_logic_vector(3 downto 0);
 
    VGA_hsync_n  : out std_logic;
 
    VGA_vsync_n  : out std_logic;
 
 
 
    -- HDMI output
 
--  TMDSp_clock  : out std_logic;
 
--  TMDSn_clock  : out std_logic;
 
--  TMDSp        : out std_logic_vector(2 downto 0);
 
--  TMDSn        : out std_logic_vector(2 downto 0);
 
 
    -- RS232 Port - via Pmod RS232
    -- RS232 Port - via Pmod RS232
--  RS232_CTS    : in  Std_Logic;
--  RS232_CTS    : in  Std_Logic;
--  RS232_RTS    : out Std_Logic;
--  RS232_RTS    : out Std_Logic;
    RS232_RXD    : in  Std_Logic;
    RS232_RXD    : in  Std_Logic;
    RS232_TXD    : out Std_Logic;
    RS232_TXD    : out Std_Logic;
Line 171... Line 188...
  constant CLOCK_MODE           : natural := 0; -- 0 means normal, 1 means single-step
  constant CLOCK_MODE           : natural := 0; -- 0 means normal, 1 means single-step
 
 
  constant SYS_CLK_FREQ         : natural := 100_000_000;  -- FPGA System Clock (in Hz)
  constant SYS_CLK_FREQ         : natural := 100_000_000;  -- FPGA System Clock (in Hz)
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
 
  constant VGA_CLK_FREQ         : natural := 25_000_000;  -- VGA Pixel Clock
 
  constant VGA_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
 
 
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Signals
  -- Signals
Line 197... Line 216...
  signal TXD            : Std_Logic;
  signal TXD            : Std_Logic;
  signal DCD_n          : Std_Logic;
  signal DCD_n          : Std_Logic;
  signal RTS_n          : Std_Logic;
  signal RTS_n          : Std_Logic;
  signal CTS_n          : Std_Logic;
  signal CTS_n          : Std_Logic;
 
 
 
  -- keyboard port
 
  signal keyboard_data_out : std_logic_vector(7 downto 0);
 
  signal keyboard_cs       : std_logic;
 
  signal keyboard_irq      : std_logic;
 
 
  -- RAM
  -- RAM
  signal ram1_cs         : std_logic;
  signal ram1_cs         : std_logic;
  signal ram1_data_out   : std_logic_vector(7 downto 0);
  signal ram1_data_out   : std_logic_vector(7 downto 0);
  signal ram2_cs         : std_logic;
  signal ram2_cs         : std_logic;
  signal ram2_data_out   : std_logic_vector(7 downto 0);
  signal ram2_data_out   : std_logic_vector(7 downto 0);
Line 222... Line 246...
 
 
  -- Dynamic Address Translation
  -- Dynamic Address Translation
  signal dat_cs       : std_logic;
  signal dat_cs       : std_logic;
  signal dat_addr     : std_logic_vector(7 downto 0);
  signal dat_addr     : std_logic_vector(7 downto 0);
 
 
 
  -- Video Display Unit
 
  signal vdu_clk        : std_logic;
 
  signal vdu_cs         : std_logic;
 
  signal vdu_data_out   : std_logic_vector(7 downto 0);
 
  signal vdu_red        : std_logic;
 
  signal vdu_green      : std_logic;
 
  signal vdu_blue       : std_logic;
 
  signal vdu_hsync      : std_logic;
 
  signal vdu_vsync      : std_logic;
 
 
  -- timer
  -- timer
  signal timer_data_out : std_logic_vector(7 downto 0);
  signal timer_data_out : std_logic_vector(7 downto 0);
  signal timer_cs       : std_logic;
  signal timer_cs       : std_logic;
  signal timer_irq      : std_logic;
  signal timer_irq      : std_logic;
 
 
Line 384... Line 418...
  );
  );
end component;
end component;
 
 
----------------------------------------
----------------------------------------
--
--
 
-- PS/2 Keyboard
 
--
 
----------------------------------------
 
 
 
component keyboard
 
  generic(
 
    KBD_CLK_FREQ : integer := CPU_CLK_FREQ
 
  );
 
  port(
 
    clk             : in    std_logic;
 
    rst             : in    std_logic;
 
    cs              : in    std_logic;
 
    rw              : in    std_logic;
 
    addr            : in    std_logic;
 
    data_in         : in    std_logic_vector(7 downto 0);
 
    data_out        : out   std_logic_vector(7 downto 0);
 
    irq             : out   std_logic;
 
    kbd_clk         : inout std_logic;
 
    kbd_data        : inout std_logic
 
  );
 
end component;
 
 
 
 
 
----------------------------------------
 
--
 
-- Video Display Unit.
 
--
 
----------------------------------------
 
 
 
component vdu8
 
  generic(
 
    VDU_CLK_FREQ           : integer := CPU_CLK_FREQ; -- HZ
 
    VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
 
    VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
 
    VGA_VER_CHARS          : integer := 25; -- CHARACTERS
 
    VGA_PIX_PER_CHAR       : integer := 8;  -- PIXELS
 
    VGA_LIN_PER_CHAR       : integer := 16; -- LINES
 
    VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
 
    VGA_HOR_SYNC           : integer := 96; -- PIXELS
 
    VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
 
    VGA_VER_BACK_PORCH     : integer := 13; -- LINES
 
    VGA_VER_SYNC           : integer := 2;  -- LINES
 
    VGA_VER_FRONT_PORCH    : integer := 35  -- LINES
 
  );
 
  port(
 
    -- control register interface
 
    vdu_clk      : in  std_logic;  -- CPU Clock - 25MHz
 
    vdu_rst      : in  std_logic;
 
    vdu_cs       : in  std_logic;
 
    vdu_rw       : in  std_logic;
 
    vdu_addr     : in  std_logic_vector(2 downto 0);
 
    vdu_data_in  : in  std_logic_vector(7 downto 0);
 
    vdu_data_out : out std_logic_vector(7 downto 0);
 
 
 
    -- vga port connections
 
    vga_clk      : in  std_logic; -- VGA Pixel Clock - 25 MHz
 
    vga_red_o    : out std_logic;
 
    vga_green_o  : out std_logic;
 
    vga_blue_o   : out std_logic;
 
    vga_hsync_o  : out std_logic;
 
    vga_vsync_o  : out std_logic
 
  );
 
end component;
 
 
 
----------------------------------------
 
--
-- Timer module
-- Timer module
--
--
----------------------------------------
----------------------------------------
 
 
component timer
component timer
Line 592... Line 692...
      acia_clk   => acia_clk
      acia_clk   => acia_clk
    );
    );
 
 
  ----------------------------------------
  ----------------------------------------
  --
  --
 
  -- PS/2 Keyboard Interface
 
  --
 
  ----------------------------------------
 
  my_keyboard : keyboard
 
    generic map (
 
      KBD_CLK_FREQ => CPU_CLK_FREQ
 
    )
 
    port map(
 
      clk          => cpu_clk,
 
      rst          => cpu_reset,
 
      cs           => keyboard_cs,
 
      rw           => cpu_rw,
 
      addr         => cpu_addr(0),
 
      data_in      => cpu_data_out(7 downto 0),
 
      data_out     => keyboard_data_out(7 downto 0),
 
      irq          => keyboard_irq,
 
      kbd_clk      => ps2_clk,
 
      kbd_data     => ps2_dat
 
    );
 
 
 
  ----------------------------------------
 
  --
 
  -- Video Display Unit instantiation
 
  --
 
  ----------------------------------------
 
  vdu_clk_buffer : BUFG
 
    port map(
 
      i => Clk25,
 
      o => vdu_clk
 
    );
 
 
 
  my_vdu : vdu8
 
    generic map(
 
      VDU_CLK_FREQ           => CPU_CLK_FREQ, -- HZ
 
      VGA_CLK_FREQ           => VGA_CLK_FREQ, -- HZ
 
      VGA_HOR_CHARS          => 80, -- CHARACTERS
 
      VGA_VER_CHARS          => 25, -- CHARACTERS
 
      VGA_PIX_PER_CHAR       => 8,  -- PIXELS
 
      VGA_LIN_PER_CHAR       => 16, -- LINES
 
      VGA_HOR_BACK_PORCH     => 40, -- PIXELS
 
      VGA_HOR_SYNC           => 96, -- PIXELS
 
      VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
 
      VGA_VER_BACK_PORCH     => 13, -- LINES
 
      VGA_VER_SYNC           => 2,  -- LINES
 
      VGA_VER_FRONT_PORCH    => 35  -- LINES
 
    )
 
    port map(
 
      -- Control Registers
 
      vdu_clk       => cpu_clk,               -- 12.5 MHz System Clock in
 
      vdu_rst       => cpu_reset,
 
      vdu_cs        => vdu_cs,
 
      vdu_rw        => cpu_rw,
 
      vdu_addr      => cpu_addr(2 downto 0),
 
      vdu_data_in   => cpu_data_out,
 
      vdu_data_out  => vdu_data_out,
 
      -- vga port connections
 
      vga_clk       => vdu_clk,               -- 25 MHz VDU pixel clock
 
      vga_red_o     => vdu_red,
 
      vga_green_o   => vdu_green,
 
      vga_blue_o    => vdu_blue,
 
      vga_hsync_o   => vdu_hsync,
 
      vga_vsync_o   => vdu_vsync
 
   );
 
 
 
  --
 
  -- VGA ouputs
 
  --
 
  my_vga_assignments : process( vdu_red, vdu_green, vdu_blue )
 
  begin
 
    VGA_green(0) <= vdu_green;
 
    VGA_green(1) <= vdu_green;
 
    VGA_green(2) <= vdu_green;
 
    VGA_green(3) <= vdu_green;
 
  end process;
 
  VGA_hsync_n <= vdu_hsync;
 
  VGA_vsync_n <= vdu_vsync;
 
 
 
  ----------------------------------------
 
  --
  -- Timer Module
  -- Timer Module
  --
  --
  ----------------------------------------
  ----------------------------------------
  my_timer  : timer
  my_timer  : timer
    port map (
    port map (
Line 654... Line 833...
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
                     dat_addr,
                     dat_addr,
                     rom_data_out,
                     rom_data_out,
                     flex_data_out,
                     flex_data_out,
                     acia_data_out,
                     acia_data_out,
 
                     keyboard_data_out,
 
                     vdu_data_out,
                     timer_data_out,
                     timer_data_out,
                     trap_data_out,
                     trap_data_out,
                     ram1_data_out, ram2_data_out
                     ram1_data_out, ram2_data_out
                     )
                     )
  begin
  begin
    cpu_data_in <= (others=>'0');
    cpu_data_in <= (others=>'0');
    dat_cs      <= '0';
    dat_cs      <= '0';
    rom_cs      <= '0';
    rom_cs      <= '0';
    flex_cs     <= '0';
    flex_cs     <= '0';
    acia_cs     <= '0';
    acia_cs     <= '0';
 
    keyboard_cs <= '0';
 
    vdu_cs      <= '0';
    timer_cs    <= '0';
    timer_cs    <= '0';
    trap_cs     <= '0';
    trap_cs     <= '0';
    ram1_cs     <= '0';
    ram1_cs     <= '0';
    ram2_cs     <= '0';
    ram2_cs     <= '0';
    ram3_cs     <= '0';
    ram3_cs     <= '0';
Line 705... Line 888...
            -- Reserved
            -- Reserved
            -- Floppy Disk Controller port $E010 - $E01F
            -- Floppy Disk Controller port $E010 - $E01F
            --
            --
 
 
            --
            --
 
            -- Keyboard port $E020 - $E02F
 
            --
 
            when "0010" => -- $E020
 
              cpu_data_in <= keyboard_data_out;
 
              keyboard_cs <= cpu_vma;
 
 
 
            --
 
            -- VDU port $E030 - $E03F
 
            --
 
            when "0011" => -- $E030
 
              cpu_data_in <= vdu_data_out;
 
              vdu_cs      <= cpu_vma;
 
 
 
            --
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
            --
            --
            when "0100" => -- $E040
            when "0100" => -- $E040
              cpu_data_in <= (others=> '0');
              cpu_data_in <= (others=> '0');
 
 
Line 782... Line 979...
  --
  --
  -- Interrupts and other bus control signals
  -- Interrupts and other bus control signals
  --
  --
  interrupts : process( NMI,
  interrupts : process( NMI,
                      acia_irq,
                      acia_irq,
 
                      keyboard_irq,
                      trap_irq,
                      trap_irq,
                      timer_irq
                      timer_irq
                      )
                      )
  begin
  begin
    cpu_irq    <= acia_irq;
    cpu_irq    <= acia_irq or keyboard_irq;
    cpu_nmi    <= trap_irq or NMI;
    cpu_nmi    <= trap_irq or NMI;
    cpu_firq   <= timer_irq;
    cpu_firq   <= timer_irq;
    cpu_halt   <= '0';
    cpu_halt   <= '0';
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
  end process;
  end process;

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