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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Diff between revs 209 and 212

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Rev 209 Rev 212
Line 134... Line 134...
 
 
    -- PS/2 Keyboard
    -- PS/2 Keyboard
    ps2_clk      : inout Std_logic;
    ps2_clk      : inout Std_logic;
    ps2_dat      : inout Std_Logic;
    ps2_dat      : inout Std_Logic;
 
 
    -- VGA port output
 
--  VGA_red      : out std_logic_vector(3 downto 0);
 
    VGA_green    : out std_logic_vector(3 downto 0);
 
--  VGA_blue     : out std_logic_vector(3 downto 0);
 
    VGA_hsync_n  : out std_logic;
 
    VGA_vsync_n  : out std_logic;
 
 
 
    -- HDMI output
    -- HDMI output
--  TMDSp_clock  : out std_logic;
    TMDSp_clock  : out std_logic;
--  TMDSn_clock  : out std_logic;
    TMDSn_clock  : out std_logic;
--  TMDSp        : out std_logic_vector(2 downto 0);
    TMDSp        : out std_logic_vector(2 downto 0);
--  TMDSn        : out std_logic_vector(2 downto 0);
    TMDSn        : out std_logic_vector(2 downto 0);
 
 
    -- RS232 Port - via Pmod RS232
    -- RS232 Port - via Atlys UART over USB (no h/w/ handshake available)
--  RS232_CTS    : in  Std_Logic;
--  RS232_CTS    : in  Std_Logic;
--  RS232_RTS    : out Std_Logic;
--  RS232_RTS    : out Std_Logic;
    RS232_RXD    : in  Std_Logic;
    RS232_RXD    : in  Std_Logic;
    RS232_TXD    : out Std_Logic;
    RS232_TXD    : out Std_Logic;
 
 
Line 250... Line 243...
 
 
  -- Video Display Unit
  -- Video Display Unit
  signal vdu_clk        : std_logic;
  signal vdu_clk        : std_logic;
  signal vdu_cs         : std_logic;
  signal vdu_cs         : std_logic;
  signal vdu_data_out   : std_logic_vector(7 downto 0);
  signal vdu_data_out   : std_logic_vector(7 downto 0);
  signal vdu_red        : std_logic;
 
  signal vdu_green      : std_logic;
 
  signal vdu_blue       : std_logic;
 
  signal vdu_hsync      : std_logic;
 
  signal vdu_vsync      : std_logic;
 
 
 
  -- timer
  -- timer
  signal timer_data_out : std_logic_vector(7 downto 0);
  signal timer_data_out : std_logic_vector(7 downto 0);
  signal timer_cs       : std_logic;
  signal timer_cs       : std_logic;
  signal timer_irq      : std_logic;
  signal timer_irq      : std_logic;
Line 440... Line 428...
    kbd_clk         : inout std_logic;
    kbd_clk         : inout std_logic;
    kbd_data        : inout std_logic
    kbd_data        : inout std_logic
  );
  );
end component;
end component;
 
 
 
 
----------------------------------------
----------------------------------------
--
--
-- Video Display Unit.
-- Video Display Unit.
--
--
----------------------------------------
----------------------------------------
 
 
component vdu8
component vdu8_hdmi
  generic(
  generic(
    VDU_CLK_FREQ           : integer := CPU_CLK_FREQ; -- HZ
    VDU_CLK_FREQ           : integer := CPU_CLK_FREQ; -- HZ
    VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
    VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
    VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
    VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
    VGA_VER_CHARS          : integer := 25; -- CHARACTERS
    VGA_VER_CHARS          : integer := 25; -- CHARACTERS
Line 471... Line 458...
    vdu_cs       : in  std_logic;
    vdu_cs       : in  std_logic;
    vdu_rw       : in  std_logic;
    vdu_rw       : in  std_logic;
    vdu_addr     : in  std_logic_vector(2 downto 0);
    vdu_addr     : in  std_logic_vector(2 downto 0);
    vdu_data_in  : in  std_logic_vector(7 downto 0);
    vdu_data_in  : in  std_logic_vector(7 downto 0);
    vdu_data_out : out std_logic_vector(7 downto 0);
    vdu_data_out : out std_logic_vector(7 downto 0);
 
    -- HDMI TMDS outputs
    -- vga port connections
         hdmi_clk     : in std_logic;
    vga_clk      : in  std_logic; -- VGA Pixel Clock - 25 MHz
    TMDSp_clock  : out std_logic;
    vga_red_o    : out std_logic;
    TMDSn_clock  : out std_logic;
    vga_green_o  : out std_logic;
    TMDSp        : out std_logic_vector(2 downto 0);
    vga_blue_o   : out std_logic;
    TMDSn        : out std_logic_vector(2 downto 0)
    vga_hsync_o  : out std_logic;
 
    vga_vsync_o  : out std_logic
 
  );
  );
end component;
end component;
 
 
----------------------------------------
----------------------------------------
--
--
Line 723... Line 708...
    port map(
    port map(
      i => Clk25,
      i => Clk25,
      o => vdu_clk
      o => vdu_clk
    );
    );
 
 
  my_vdu : vdu8
  my_vdu : vdu8_hdmi
    generic map(
    generic map(
      VDU_CLK_FREQ           => CPU_CLK_FREQ, -- HZ
      VDU_CLK_FREQ           => CPU_CLK_FREQ, -- HZ
      VGA_CLK_FREQ           => VGA_CLK_FREQ, -- HZ
      VGA_CLK_FREQ           => VGA_CLK_FREQ, -- HZ
      VGA_HOR_CHARS          => 80, -- CHARACTERS
      VGA_HOR_CHARS          => 80, -- CHARACTERS
      VGA_VER_CHARS          => 25, -- CHARACTERS
      VGA_VER_CHARS          => 25, -- CHARACTERS
Line 747... Line 732...
      vdu_cs        => vdu_cs,
      vdu_cs        => vdu_cs,
      vdu_rw        => cpu_rw,
      vdu_rw        => cpu_rw,
      vdu_addr      => cpu_addr(2 downto 0),
      vdu_addr      => cpu_addr(2 downto 0),
      vdu_data_in   => cpu_data_out,
      vdu_data_in   => cpu_data_out,
      vdu_data_out  => vdu_data_out,
      vdu_data_out  => vdu_data_out,
      -- vga port connections
                -- HDMI port connections
      vga_clk       => vdu_clk,               -- 25 MHz VDU pixel clock
                hdmi_clk    => Clk25,
      vga_red_o     => vdu_red,
                TMDSp       => TMDSp,
      vga_green_o   => vdu_green,
                TMDSn       => TMDSn,
      vga_blue_o    => vdu_blue,
                TMDSp_clock => TMDSp_clock,
      vga_hsync_o   => vdu_hsync,
                TMDSn_clock => TMDSn_clock
      vga_vsync_o   => vdu_vsync
 
   );
   );
 
 
  --
 
  -- VGA ouputs
 
  --
 
  my_vga_assignments : process( vdu_red, vdu_green, vdu_blue )
 
  begin
 
    VGA_green(0) <= vdu_green;
 
    VGA_green(1) <= vdu_green;
 
    VGA_green(2) <= vdu_green;
 
    VGA_green(3) <= vdu_green;
 
  end process;
 
  VGA_hsync_n <= vdu_hsync;
 
  VGA_vsync_n <= vdu_vsync;
 
 
 
  ----------------------------------------
  ----------------------------------------
  --
  --
  -- Timer Module
  -- Timer Module
  --
  --

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