| Line 126... |
Line 126... |
library unisim;
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library unisim;
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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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|
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entity system09 is
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entity system09 is
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port(
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port(
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CLKA : in Std_Logic; -- 100MHz Clock input
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sysclk : in Std_Logic; -- 100MHz Clock input
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SW2_N : in Std_logic; -- Master Reset input (active low)
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RESET_N : in Std_logic; -- Master Reset input (active low)
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SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low)
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NMI_N : in Std_logic; -- Non Maskable Interrupt input (active low)
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-- RS232 Port
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-- RS232 Port
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RS232_RXD : in Std_Logic;
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--RS232_CTS : in std_logic;
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RS232_TXD : out Std_Logic;
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--RS232_RTS : out std_logic;
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RS232_RXD : in Std_Logic; -- RS-232 data in
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-- Status 7 segment LED
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RS232_TXD : out Std_Logic -- RS-232 data out
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S : out std_logic_vector(7 downto 0)
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|
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-- CPU Debug Interface signals
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-- CPU Debug Interface signals
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-- cpu_reset_o : out Std_Logic;
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-- cpu_reset_o : out Std_Logic;
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-- cpu_clk_o : out Std_Logic;
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-- cpu_clk_o : out Std_Logic;
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-- cpu_rw_o : out std_logic;
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-- cpu_rw_o : out std_logic;
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| Line 162... |
Line 161... |
architecture rtl of system09 is
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architecture rtl of system09 is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- constants
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-- constants
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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constant SYS_CLK_FREQ : natural := 100_000_000; -- FPGA System Clock (in Hz)
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-- SDRAM
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constant MEM_CLK_FREQ : natural := 100_000; -- operating frequency of Memory in KHz
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constant SYS_CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
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constant PIPE_EN : boolean := false; -- if true, enable pipelined read operations
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constant MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh
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constant MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank
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constant DATA_WIDTH : natural := 16; -- host & SDRAM data width
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constant NROWS : natural := 8192; -- number of rows in SDRAM array
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constant NCOLS : natural := 512; -- number of columns in SDRAM array
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constant HADDR_WIDTH : natural := 24; -- host-side address width
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constant SADDR_WIDTH : natural := 13; -- SDRAM-side address width
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constant SYS_CLK_FREQ : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000; -- FPGA System Clock
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constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
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constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
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constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
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constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
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constant BAUD_RATE : integer := 57600; -- Baud Rate
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constant BAUD_RATE : integer := 57600; -- Baud Rate
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constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
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constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
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constant TRESET : natural := 300; -- min initialization interval (us)
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constant RST_CYCLES : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000)); -- SDRAM power-on initialization interval
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type hold_state_type is ( hold_release_state, hold_request_state );
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Signals
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-- Signals
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- BOOT ROM
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-- BOOT ROM
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signal rom_cs : Std_logic;
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signal rom_cs : Std_logic;
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signal rom_data_out : Std_Logic_Vector(7 downto 0);
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signal rom_data_out : Std_Logic_Vector(7 downto 0);
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-- Flex Memory & Monitor Stack
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-- Flex Memory & Monitor Stack
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| Line 209... |
Line 191... |
signal DCD_n : Std_Logic;
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signal DCD_n : Std_Logic;
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signal RTS_n : Std_Logic;
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signal RTS_n : Std_Logic;
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signal CTS_n : Std_Logic;
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signal CTS_n : Std_Logic;
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-- RAM
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-- RAM
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signal ram_cs : std_logic; -- memory chip select
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signal ram1_cs : std_logic;
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signal ram_data_out : std_logic_vector(7 downto 0);
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signal ram1_data_out : std_logic_vector(7 downto 0);
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signal ram_rd_req : std_logic; -- ram read request (asynch set on ram read, cleared falling CPU clock edge)
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signal ram2_cs : std_logic;
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signal ram_wr_req : std_logic; -- ram write request (set on rising CPU clock edge, asynch clear on acknowledge)
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signal ram2_data_out : std_logic_vector(7 downto 0);
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signal ram_hold : std_logic; -- hold off slow accesses
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signal ram3_cs : std_logic;
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signal ram_release : std_logic; -- Release ram hold
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-- CPU Interface signals
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-- CPU Interface signals
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signal cpu_reset : Std_Logic;
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signal cpu_reset : Std_Logic;
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signal cpu_clk : Std_Logic;
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signal cpu_clk : Std_Logic;
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signal cpu_rw : std_logic;
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signal cpu_rw : std_logic;
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| Line 244... |
Line 225... |
-- trap
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-- trap
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signal trap_cs : std_logic;
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signal trap_cs : std_logic;
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signal trap_data_out : std_logic_vector(7 downto 0);
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signal trap_data_out : std_logic_vector(7 downto 0);
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signal trap_irq : std_logic;
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signal trap_irq : std_logic;
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-- Peripheral Bus port
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signal pb_data_out : std_logic_vector(7 downto 0);
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signal pb_cs : std_logic; -- peripheral bus chip select
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signal pb_wru : std_logic; -- upper byte write strobe
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signal pb_wrl : std_logic; -- lower byte write strobe
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signal pb_rdu : std_logic; -- upper byte read strobe
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signal pb_rdl : std_logic; -- lower byte read strobe
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signal pb_hold : std_logic; -- hold peripheral bus access
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signal pb_release : std_logic; -- release hold of peripheral bus
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signal pb_count : std_logic_vector(3 downto 0); -- hold counter
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signal pb_hold_state : hold_state_type;
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signal pb_wreg : std_logic_vector(7 downto 0); -- lower byte write register
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signal pb_rreg : std_logic_vector(7 downto 0); -- lower byte read register
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signal rst_i : std_logic; -- internal reset signal
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signal rst_i : std_logic; -- internal reset signal
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signal clk_i : std_logic; -- internal master clock signal
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signal clk_i : std_logic; -- internal master clock signal
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-- signals that go through the SDRAM host-side interface
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signal opBegun : std_logic; -- SDRAM operation started indicator
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signal earlyBegun : std_logic; -- SDRAM operation started indicator
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signal ramDone : std_logic; -- SDRAM operation complete indicator
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signal rdDone : std_logic; -- SDRAM read operation complete indicator
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signal wrDone : std_logic; -- SDRAM write operation complete indicator
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signal hAddr : std_logic_vector(HADDR_WIDTH-1 downto 0); -- host address bus
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signal hDIn : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data to SDRAM
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signal hDOut : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data from SDRAM
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signal hRd : std_logic; -- host-side read control signal
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signal hWr : std_logic; -- host-side write control signal
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signal hUds : std_logic; -- host-side upper data strobe
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signal hLds : std_logic; -- host-side lower data strobe
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signal rdPending : std_logic; -- read operation pending in SDRAM pipeline
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type ram_type is (ram_state_0,
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ram_state_rd1, ram_state_rd2,
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ram_state_wr1,
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ram_state_3 );
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signal ram_state : ram_type;
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signal flash_ce_n : std_logic;
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signal rs232_cts : Std_Logic;
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signal rs232_cts : Std_Logic;
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signal rs232_rts : Std_Logic;
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signal rs232_rts : Std_Logic;
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-- signal BaudCount : std_logic_vector(5 downto 0);
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signal CountL : std_logic_vector(23 downto 0);
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signal clk_count : natural range 0 to CPU_CLK_DIV;
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signal clk_count : natural range 0 to CPU_CLK_DIV;
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signal Clk25 : std_logic;
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signal Clk25 : std_logic;
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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--
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--
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| Line 352... |
Line 295... |
data_out : out std_logic_vector (7 downto 0);
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data_out : out std_logic_vector (7 downto 0);
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data_in : in std_logic_vector (7 downto 0)
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data_in : in std_logic_vector (7 downto 0)
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);
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);
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end component;
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end component;
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----------------------------------------
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--
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-- 32KBytes Block RAM 0000
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-- $0000 - $7FFF
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--
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----------------------------------------
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component ram_32k
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Port (
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clk : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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rw : in std_logic;
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addr : in std_logic_vector (14 downto 0);
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data_out : out std_logic_vector (7 downto 0);
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data_in : in std_logic_vector (7 downto 0)
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);
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end component;
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----------------------------------------
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--
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-- 16KBytes Block RAM 8000
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-- $8000 - $BFFF
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--
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----------------------------------------
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component ram_16k
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Port (
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clk : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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rw : in std_logic;
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addr : in std_logic_vector (13 downto 0);
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data_out : out std_logic_vector (7 downto 0);
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data_in : in std_logic_vector (7 downto 0)
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);
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end component;
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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--
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--
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-- 6850 Compatible ACIA / UART
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-- 6850 Compatible ACIA / UART
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--
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--
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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| Line 453... |
Line 435... |
data_in : in std_logic_vector(7 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0)
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data_out : out std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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----------------------------------------
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--
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--
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-- Clock buffer
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-- Clock buffer
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--
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--
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----------------------------------------
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component BUFG
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component BUFG
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Port (
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Port (
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i: in std_logic;
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i: in std_logic;
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o: out std_logic
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o: out std_logic
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);
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);
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end component;
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end component;
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begin
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begin
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clk_i <= sysclk;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Instantiation of internal components
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-- Instantiation of internal components
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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my_cpu : cpu09
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my_cpu : cpu09
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| Line 509... |
Line 493... |
addr => cpu_addr(12 downto 0),
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addr => cpu_addr(12 downto 0),
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data_out => flex_data_out,
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data_out => flex_data_out,
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data_in => cpu_data_out
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data_in => cpu_data_out
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);
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);
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my_32k : ram_32k
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port map (
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clk => cpu_clk,
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rst => cpu_reset,
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cs => ram1_cs,
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rw => cpu_rw,
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addr => cpu_addr(14 downto 0),
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data_out => ram1_data_out,
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data_in => cpu_data_out
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);
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my_16k : ram_16k
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port map (
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clk => cpu_clk,
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rst => cpu_reset,
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cs => ram2_cs,
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rw => cpu_rw,
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addr => cpu_addr(13 downto 0),
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data_out => ram2_data_out,
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data_in => cpu_data_out
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);
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my_acia : acia6850
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my_acia : acia6850
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port map (
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port map (
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clk => cpu_clk,
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clk => cpu_clk,
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rst => cpu_reset,
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rst => cpu_reset,
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cs => acia_cs,
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cs => acia_cs,
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| Line 602... |
Line 608... |
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
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mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
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dat_addr,
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dat_addr,
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rom_data_out,
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rom_data_out,
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flex_data_out,
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flex_data_out,
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acia_data_out,
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acia_data_out,
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pb_data_out,
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timer_data_out,
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timer_data_out,
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trap_data_out,
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trap_data_out,
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ram_data_out
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ram1_data_out, ram2_data_out
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)
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)
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begin
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begin
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cpu_data_in <= (others=>'0');
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cpu_data_in <= (others=>'0');
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dat_cs <= '0';
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dat_cs <= '0';
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rom_cs <= '0';
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rom_cs <= '0';
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flex_cs <= '0';
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flex_cs <= '0';
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acia_cs <= '0';
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acia_cs <= '0';
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timer_cs <= '0';
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timer_cs <= '0';
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trap_cs <= '0';
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trap_cs <= '0';
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pb_cs <= '0';
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ram1_cs <= '0';
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ram_cs <= '0';
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ram2_cs <= '0';
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|
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if cpu_addr( 15 downto 8 ) = "11111111" then -- $FFxx
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if cpu_addr( 15 downto 8 ) = "11111111" then -- $FFxx
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cpu_data_in <= rom_data_out;
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cpu_data_in <= rom_data_out;
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dat_cs <= cpu_vma; -- write DAT
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dat_cs <= cpu_vma; -- write DAT
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rom_cs <= cpu_vma; -- read ROM
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rom_cs <= cpu_vma; -- read ROM
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| Line 702... |
Line 707... |
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
|
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
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cpu_data_in <= flex_data_out;
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cpu_data_in <= flex_data_out;
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flex_cs <= cpu_vma;
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flex_cs <= cpu_vma;
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|
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--
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--
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-- 32k RAM $00000 - $07FFF
|
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--
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elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF
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cpu_data_in <= ram1_data_out;
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ram1_cs <= cpu_vma;
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|
|
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--
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-- 16k RAM $08000 - $0BFFF
|
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--
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elsif dat_addr(7 downto 1) = "0000100" then -- $08000 - $0BFFF
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cpu_data_in <= ram2_data_out;
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ram2_cs <= cpu_vma;
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|
|
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--
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-- Everything else is RAM
|
-- Everything else is RAM
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--
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--
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else
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else
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cpu_data_in <= ram_data_out;
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cpu_data_in <= (others => '0');
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ram_cs <= cpu_vma;
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ram3_cs <= cpu_vma;
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end if;
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end if;
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|
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end process;
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end process;
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|
|
--
|
--
|
-- Interrupts and other bus control signals
|
-- Interrupts and other bus control signals
|
--
|
--
|
interrupts : process( SW3_N,
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interrupts : process( NMI_N,
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pb_cs, pb_hold, pb_release, ram_hold,
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acia_irq,
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acia_irq,
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trap_irq,
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trap_irq,
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timer_irq
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timer_irq
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)
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)
|
begin
|
begin
|
pb_hold <= pb_cs and (not pb_release);
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cpu_irq <= acia_irq;
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cpu_irq <= acia_irq;
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cpu_nmi <= trap_irq or not( SW3_N );
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cpu_nmi <= trap_irq or not( NMI_N );
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cpu_firq <= timer_irq;
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cpu_firq <= timer_irq;
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cpu_halt <= '0';
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cpu_halt <= '0';
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cpu_hold <= pb_hold or ram_hold;
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cpu_hold <= '0'; -- pb_hold or ram_hold;
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FLASH_CE_N <= '1';
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end process;
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|
|
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--
|
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-- Flash 7 segment LEDS
|
|
--
|
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my_led_flasher: process( clk_i, rst_i, CountL )
|
|
begin
|
|
if rst_i = '1' then
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CountL <= "000000000000000000000000";
|
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elsif rising_edge(clk_i) then
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CountL <= CountL + 1;
|
|
end if;
|
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--S(7 downto 0) <= CountL(23 downto 16);
|
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end process;
|
end process;
|
|
|
--
|
--
|
-- Generate CPU & Pixel Clock from Memory Clock
|
-- Generate CPU & Pixel Clock from Memory Clock
|
--
|
--
|
| Line 765... |
Line 768... |
end process;
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end process;
|
|
|
--
|
--
|
-- Reset button and reset timer
|
-- Reset button and reset timer
|
--
|
--
|
my_switch_assignments : process( rst_i, SW2_N)
|
my_switch_assignments : process( rst_i, RESET_N)
|
begin
|
begin
|
rst_i <= not SW2_N;
|
rst_i <= RESET_N;
|
cpu_reset <= rst_i;
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cpu_reset <= rst_i;
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end process;
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end process;
|
|
|
--
|
--
|
-- RS232 signals:
|
-- RS232 signals:
|
| Line 783... |
Line 786... |
dcd_n <= '0';
|
dcd_n <= '0';
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RS232_TXD <= txd;
|
RS232_TXD <= txd;
|
RS232_RTS <= rts_n;
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RS232_RTS <= rts_n;
|
end process;
|
end process;
|
|
|
--
|
|
-- CPU read data request on rising CPU clock edge
|
|
--
|
|
ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release )
|
|
begin
|
|
if hRd = '1' then
|
|
ram_rd_req <= '0';
|
|
elsif rising_edge(cpu_clk) then
|
|
if (ram_cs = '1') and (cpu_rw = '1') and (ram_release = '1') then
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ram_rd_req <= '1';
|
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end if;
|
|
end if;
|
|
end process;
|
|
|
|
--
|
|
-- CPU write data to RAM valid on rising CPU clock edge
|
|
--
|
|
ram_write_request: process( hWr, cpu_clk, ram_cs, cpu_rw, ram_release )
|
|
begin
|
|
if hWr = '1' then
|
|
ram_wr_req <= '0';
|
|
elsif rising_edge(cpu_clk) then
|
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if (ram_cs = '1') and (cpu_rw = '0') and (ram_release = '1') then
|
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ram_wr_req <= '1';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
status_leds : process( rst_i, cpu_reset)
|
|
begin
|
|
S(7) <= rst_i;
|
|
S(6) <= cpu_reset;
|
|
S(2) <= countL(23);
|
|
S(3) <= countL(22);
|
|
S(4) <= countL(21);
|
|
S(5) <= countL(20);
|
|
S(1) <= '1'; -- countL(19);
|
|
S(0) <= '0'; -- countL(18);
|
|
--S(7 downto 4) <= "0000";
|
|
end process;
|
|
|
|
-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
|
-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
|
-- cpu_halt, cpu_hold,
|
-- cpu_halt, cpu_hold,
|
-- cpu_firq, cpu_irq, cpu_nmi,
|
-- cpu_firq, cpu_irq, cpu_nmi,
|
-- cpu_addr, cpu_data_out, cpu_data_in )
|
-- cpu_addr, cpu_data_out, cpu_data_in )
|
-- begin
|
-- begin
|
