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https://opencores.org/ocsvn/System09/System09/trunk
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entity system09 is
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entity system09 is
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port(
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port(
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CLKA : in Std_Logic; -- 125 MHz Clock input
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CLKA : in Std_Logic; -- 125 MHz Clock input
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-- RS232 Port - via Pmod RS232
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-- RS232 Port - via Pmod RS232
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-- RS232_CTS : in Std_Logic;
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RS232_CTS : in Std_Logic;
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-- RS232_RTS : out Std_Logic;
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RS232_RTS : out Std_Logic;
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RS232_RXD : in Std_Logic;
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RS232_RXD : in Std_Logic;
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RS232_TXD : out Std_Logic;
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RS232_TXD : out Std_Logic;
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-- slide switches
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-- slide switches
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sw : in std_logic_vector(3 downto 0);
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sw : in std_logic_vector(3 downto 0);
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Line 523... |
Line 523... |
);
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);
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--
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--
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-- RS232 signals:
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-- RS232 signals:
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--
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--
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my_acia_assignments : process( RS232_RXD, --RS232_CTS,
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my_acia_assignments : process( RS232_RXD, RS232_CTS,
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TXD, RTS_n )
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TXD, RTS_n )
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begin
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begin
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RXD <= RS232_RXD;
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RXD <= RS232_RXD;
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CTS_n <= '0'; -- not RS232_CTS;
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CTS_n <= RS232_CTS;
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DCD_n <= '0';
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DCD_n <= '0';
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RS232_TXD <= TXD;
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RS232_TXD <= TXD;
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-- RS232_RTS <= not RTS_n;
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RS232_RTS <= RTS_n;
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end process;
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end process;
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my_ACIA_Clock : ACIA_Clock
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my_ACIA_Clock : ACIA_Clock
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generic map(
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generic map(
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SYS_CLK_FREQ => SYS_CLK_FREQ,
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SYS_CLK_FREQ => SYS_CLK_FREQ,
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