Line 81... |
Line 81... |
RS232_CTS : in Std_Logic;
|
RS232_CTS : in Std_Logic;
|
RS232_RTS : out Std_Logic;
|
RS232_RTS : out Std_Logic;
|
RS232_RXD : in Std_Logic;
|
RS232_RXD : in Std_Logic;
|
RS232_TXD : out Std_Logic;
|
RS232_TXD : out Std_Logic;
|
|
|
|
-- TMDS_Clk_p : out std_logic;
|
|
-- TMDS_Clk_n : out std_logic;
|
|
-- TMDS_Data_p : out std_logic_vector(2 downto 0);
|
|
-- TMDS_Data_n : out std_logic_vector(2 downto 0);
|
|
|
|
-- raw output from VDU8
|
|
red, green, blue, hsync, vsync, blank : out std_logic;
|
|
|
-- slide switches
|
-- slide switches
|
sw : in std_logic_vector(3 downto 0);
|
sw : in std_logic_vector(3 downto 0);
|
-- push buttons [Unused, Single-Step, NMI, RESET]
|
-- push buttons [Unused, Single-Step, NMI, RESET]
|
btn : in std_logic_vector(3 downto 0);
|
btn : in std_logic_vector(3 downto 0);
|
-- Status 4 LEDs
|
-- Status 4 LEDs
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Line 103... |
Line 111... |
constant CLOCK_MODE : natural := 0; -- 0 means normal, 1 means single-step
|
constant CLOCK_MODE : natural := 0; -- 0 means normal, 1 means single-step
|
|
|
constant SYS_CLK_FREQ : natural := 125_000_000; -- FPGA System Clock (in Hz)
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constant SYS_CLK_FREQ : natural := 125_000_000; -- FPGA System Clock (in Hz)
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constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
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constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
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constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
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constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
|
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constant VGA_CLK_FREQ : natural := 25_000_000; -- VGA Pixel Clock
|
|
constant VGA_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
|
constant BAUD_RATE : integer := 57600; -- Baud Rate
|
constant BAUD_RATE : integer := 57600; -- Baud Rate
|
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
|
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Signals
|
-- Signals
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Line 158... |
Line 168... |
|
|
-- Dynamic Address Translation
|
-- Dynamic Address Translation
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signal dat_cs : std_logic;
|
signal dat_cs : std_logic;
|
signal dat_addr : std_logic_vector(7 downto 0);
|
signal dat_addr : std_logic_vector(7 downto 0);
|
|
|
|
-- Video Display Unit (single-bit for each RGB color)
|
|
signal vdu_cs : std_logic;
|
|
signal vdu_data_out : std_logic_vector(7 downto 0);
|
|
signal vga_red_o : std_logic;
|
|
signal vga_green_o : std_logic;
|
|
signal vga_blue_o : std_logic;
|
|
signal vga_blank_o : std_logic; -- new signal
|
|
-- original VGA interface
|
|
signal vga_vsync_n : Std_Logic;
|
|
signal vga_hsync_n : Std_Logic;
|
|
signal VGA_blue : std_logic_vector(7 downto 0);
|
|
signal VGA_green : std_logic_vector(7 downto 0);
|
|
signal VGA_red : std_logic_vector(7 downto 0);
|
|
signal vid_pData : std_logic_vector(23 downto 0);
|
|
signal serial_clk_unused : std_logic;
|
-- timer
|
-- timer
|
signal timer_data_out : std_logic_vector(7 downto 0);
|
signal timer_data_out : std_logic_vector(7 downto 0);
|
signal timer_cs : std_logic;
|
signal timer_cs : std_logic;
|
signal timer_irq : std_logic;
|
signal timer_irq : std_logic;
|
|
|
Line 174... |
Line 199... |
signal clk_i : std_logic; -- internal master clock signal
|
signal clk_i : std_logic; -- internal master clock signal
|
|
|
signal CountL : std_logic_vector(25 downto 0);
|
signal CountL : std_logic_vector(25 downto 0);
|
signal clk_count : natural range 0 to CPU_CLK_DIV;
|
signal clk_count : natural range 0 to CPU_CLK_DIV;
|
signal Clk25 : std_logic;
|
signal Clk25 : std_logic;
|
|
signal vga_clk : std_logic;
|
|
|
component btn_debounce
|
component btn_debounce
|
Port ( BTN_I : in STD_LOGIC_VECTOR (3 downto 0);
|
Port ( BTN_I : in STD_LOGIC_VECTOR (3 downto 0);
|
CLK : in STD_LOGIC;
|
CLK : in STD_LOGIC;
|
BTN_O : out STD_LOGIC_VECTOR (3 downto 0));
|
BTN_O : out STD_LOGIC_VECTOR (3 downto 0));
|
Line 326... |
Line 351... |
clk : in Std_Logic; -- System Clock Input
|
clk : in Std_Logic; -- System Clock Input
|
ACIA_clk : out Std_logic -- ACIA Clock output
|
ACIA_clk : out Std_logic -- ACIA Clock output
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
|
----------------------------------------
|
|
--
|
|
-- Video Display Unit.
|
|
--
|
|
----------------------------------------
|
|
|
|
component vdu8
|
|
generic(
|
|
VDU_CLK_FREQ : integer := CPU_CLK_FREQ; -- HZ
|
|
VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- HZ
|
|
VGA_HOR_CHARS : integer := 80; -- CHARACTERS
|
|
VGA_VER_CHARS : integer := 25; -- CHARACTERS
|
|
VGA_PIX_PER_CHAR : integer := 8; -- PIXELS
|
|
VGA_LIN_PER_CHAR : integer := 16; -- LINES
|
|
VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
|
|
VGA_HOR_SYNC : integer := 96; -- PIXELS
|
|
VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
|
|
VGA_VER_BACK_PORCH : integer := 13; -- LINES
|
|
VGA_VER_SYNC : integer := 2; -- LINES
|
|
VGA_VER_FRONT_PORCH : integer := 35 -- LINES
|
|
);
|
|
port(
|
|
-- control register interface
|
|
vdu_clk : in std_logic; -- CPU Clock - 25MHz
|
|
vdu_rst : in std_logic;
|
|
vdu_cs : in std_logic;
|
|
vdu_rw : in std_logic;
|
|
vdu_addr : in std_logic_vector(2 downto 0);
|
|
vdu_data_in : in std_logic_vector(7 downto 0);
|
|
vdu_data_out : out std_logic_vector(7 downto 0);
|
|
|
|
-- vga port connections
|
|
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
|
|
vga_red_o : out std_logic;
|
|
vga_green_o : out std_logic;
|
|
vga_blue_o : out std_logic;
|
|
vga_blank_o : out std_logic; -- new signal "blank"
|
|
vga_hsync_o : out std_logic;
|
|
vga_vsync_o : out std_logic
|
|
);
|
|
end component;
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Timer module
|
-- Timer module
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
Line 545... |
Line 614... |
acia_clk => acia_clk
|
acia_clk => acia_clk
|
);
|
);
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
|
-- Video Display Unit instantiation
|
|
--
|
|
----------------------------------------
|
|
my_vdu : vdu8
|
|
generic map(
|
|
VDU_CLK_FREQ => CPU_CLK_FREQ, -- HZ
|
|
VGA_CLK_FREQ => VGA_CLK_FREQ, -- HZ
|
|
VGA_HOR_CHARS => 80, -- CHARACTERS
|
|
VGA_VER_CHARS => 25, -- CHARACTERS
|
|
VGA_PIX_PER_CHAR => 8, -- PIXELS
|
|
VGA_LIN_PER_CHAR => 16, -- LINES
|
|
VGA_HOR_BACK_PORCH => 40, -- PIXELS
|
|
VGA_HOR_SYNC => 96, -- PIXELS
|
|
VGA_HOR_FRONT_PORCH => 24, -- PIXELS
|
|
VGA_VER_BACK_PORCH => 13, -- LINES
|
|
VGA_VER_SYNC => 2, -- LINES
|
|
VGA_VER_FRONT_PORCH => 35 -- LINES
|
|
)
|
|
port map(
|
|
-- Control Registers
|
|
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
|
|
vdu_rst => cpu_reset,
|
|
vdu_cs => vdu_cs,
|
|
vdu_rw => cpu_rw,
|
|
vdu_addr => cpu_addr(2 downto 0),
|
|
vdu_data_in => cpu_data_out,
|
|
vdu_data_out => vdu_data_out,
|
|
-- vga port connections
|
|
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
|
|
vga_red_o => red,
|
|
vga_green_o => green,
|
|
vga_blue_o => blue,
|
|
vga_blank_o => blank, -- new signal
|
|
vga_hsync_o => hsync,
|
|
vga_vsync_o => vsync
|
|
);
|
|
|
|
----------------------------------------
|
|
--
|
-- Timer Module
|
-- Timer Module
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_timer : timer
|
my_timer : timer
|
port map (
|
port map (
|
Line 607... |
Line 715... |
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
|
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
|
dat_addr,
|
dat_addr,
|
rom_data_out,
|
rom_data_out,
|
flex_data_out,
|
flex_data_out,
|
acia_data_out,
|
acia_data_out,
|
|
vdu_data_out,
|
timer_data_out,
|
timer_data_out,
|
trap_data_out,
|
trap_data_out,
|
ram1_data_out, ram2_data_out
|
ram1_data_out, ram2_data_out
|
)
|
)
|
begin
|
begin
|
cpu_data_in <= (others=>'0');
|
cpu_data_in <= (others=>'0');
|
dat_cs <= '0';
|
dat_cs <= '0';
|
rom_cs <= '0';
|
rom_cs <= '0';
|
flex_cs <= '0';
|
flex_cs <= '0';
|
acia_cs <= '0';
|
acia_cs <= '0';
|
|
vdu_cs <= '0';
|
timer_cs <= '0';
|
timer_cs <= '0';
|
trap_cs <= '0';
|
trap_cs <= '0';
|
ram1_cs <= '0';
|
ram1_cs <= '0';
|
ram2_cs <= '0';
|
ram2_cs <= '0';
|
|
|
Line 655... |
Line 765... |
|
|
--
|
--
|
-- Reserved
|
-- Reserved
|
-- Floppy Disk Controller port $E010 - $E01F
|
-- Floppy Disk Controller port $E010 - $E01F
|
--
|
--
|
|
--
|
|
-- VDU port $E030 - $E03F
|
|
--
|
|
when "0011" => -- $E030
|
|
cpu_data_in <= vdu_data_out;
|
|
vdu_cs <= cpu_vma;
|
|
|
--
|
--
|
-- Reserved SWTPc MP-T Timer $E040 - $E04F
|
-- Reserved SWTPc MP-T Timer $E040 - $E04F
|
--
|
--
|
when "0100" => -- $E040
|
when "0100" => -- $E040
|