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use work.common.all;
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use work.common.all;
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use WORK.xsasdram.all;
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use WORK.xsasdram.all;
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library unisim;
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library unisim;
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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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entity my_system09 is
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entity system09 is
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port(
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port(
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CLKA : in Std_Logic; -- 100MHz Clock input
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CLKA : in Std_Logic; -- 100MHz Clock input
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SW2_N : in Std_logic; -- Master Reset input (active low)
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SW2_N : in Std_logic; -- Master Reset input (active low)
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SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low)
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SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low)
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-- slot2_irq : in std_logic;
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-- slot2_irq : in std_logic;
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-- Disable Flash
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-- Disable Flash
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FLASH_CE_N : out std_logic
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FLASH_CE_N : out std_logic
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);
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);
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end My_System09;
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end system09;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for System09
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-- Architecture for System09
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture rtl of my_system09 is
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architecture rtl of system09 is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- constants
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-- constants
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock
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constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock
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