| Line 137... |
Line 137... |
use unisim.vcomponents.all;
|
use unisim.vcomponents.all;
|
|
|
entity system09 is
|
entity system09 is
|
port(
|
port(
|
CLKA : in Std_Logic; -- 100MHz Clock input
|
CLKA : in Std_Logic; -- 100MHz Clock input
|
|
-- CLKB : in Std_Logic; -- 50MHz Clock input
|
SW2_N : in Std_logic; -- Master Reset input (active low)
|
SW2_N : in Std_logic; -- Master Reset input (active low)
|
SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low)
|
SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low)
|
|
|
-- PS/2 Keyboard
|
-- PS/2 Keyboard
|
ps2_clk : inout Std_logic;
|
ps2_clk : inout Std_logic;
|
| Line 158... |
Line 159... |
RS232_TXD : out Std_Logic;
|
RS232_TXD : out Std_Logic;
|
RS232_CTS : in Std_Logic;
|
RS232_CTS : in Std_Logic;
|
RS232_RTS : out Std_Logic;
|
RS232_RTS : out Std_Logic;
|
|
|
-- Status 7 segment LED
|
-- Status 7 segment LED
|
-- S : out std_logic_vector(7 downto 0);
|
S : out std_logic_vector(7 downto 0);
|
|
|
-- SDRAM side
|
-- SDRAM side
|
SDRAM_clkfb : in std_logic; -- feedback SDRAM clock after PCB delays
|
SDRAM_clkfb : in std_logic; -- feedback SDRAM clock after PCB delays
|
SDRAM_clkout : out std_logic; -- clock to SDRAM
|
SDRAM_clkout : out std_logic; -- clock to SDRAM
|
SDRAM_CKE : out std_logic; -- clock-enable to SDRAM
|
SDRAM_CKE : out std_logic; -- clock-enable to SDRAM
|
| Line 201... |
Line 202... |
|
|
-- Slot 2 $E1C0 - $E1FF
|
-- Slot 2 $E1C0 - $E1FF
|
slot2_cs_n : out std_logic;
|
slot2_cs_n : out std_logic;
|
-- slot2_irq : in std_logic;
|
-- slot2_irq : in std_logic;
|
|
|
|
-- CPU Debug Interface signals
|
|
-- cpu_reset_o : out Std_Logic;
|
|
-- cpu_clk_o : out Std_Logic;
|
|
-- cpu_rw_o : out std_logic;
|
|
-- cpu_vma_o : out std_logic;
|
|
-- cpu_halt_o : out std_logic;
|
|
-- cpu_hold_o : out std_logic;
|
|
-- cpu_firq_o : out std_logic;
|
|
-- cpu_irq_o : out std_logic;
|
|
-- cpu_nmi_o : out std_logic;
|
|
-- cpu_addr_o : out std_logic_vector(15 downto 0);
|
|
-- cpu_data_in_o : out std_logic_vector(7 downto 0);
|
|
-- cpu_data_out_o : out std_logic_vector(7 downto 0);
|
|
|
-- Disable Flash
|
-- Disable Flash
|
FLASH_CE_N : out std_logic
|
FLASH_CE_N : out std_logic
|
);
|
);
|
end system09;
|
end system09;
|
|
|
| Line 214... |
Line 229... |
architecture rtl of system09 is
|
architecture rtl of system09 is
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- constants
|
-- constants
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock
|
|
constant PIX_Clock_Frequency : integer := 25000000; -- VGA Pixel Clock
|
-- SDRAM
|
constant CPU_Clock_Frequency : integer := 25000000; -- CPU Clock
|
constant MEM_CLK_FREQ : natural := 100_000; -- operating frequency of Memory in KHz
|
constant BAUD_Rate : integer := 57600; -- Baud Rate
|
constant SYS_CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
|
constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
|
constant PIPE_EN : boolean := false; -- if true, enable pipelined read operations
|
|
constant MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh
|
|
constant MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank
|
|
constant DATA_WIDTH : natural := 16; -- host & SDRAM data width
|
|
constant NROWS : natural := 8192; -- number of rows in SDRAM array
|
|
constant NCOLS : natural := 512; -- number of columns in SDRAM array
|
|
constant HADDR_WIDTH : natural := 24; -- host-side address width
|
|
constant SADDR_WIDTH : natural := 13; -- SDRAM-side address width
|
|
|
|
constant SYS_CLK_FREQ : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000; -- FPGA System Clock
|
|
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
|
|
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
|
|
constant VGA_CLK_FREQ : natural := 25_000_000; -- VGA Pixel Clock
|
|
constant VGA_CLK_DIV : natural := ((MEM_CLK_FREQ*1000)/VGA_CLK_FREQ);
|
|
constant BAUD_RATE : integer := 57600; -- Baud Rate
|
|
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
|
|
|
|
constant TRESET : natural := 300; -- min initialization interval (us)
|
|
constant RST_CYCLES : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000)); -- SDRAM power-on initialization interval
|
|
|
type hold_state_type is ( hold_release_state, hold_request_state );
|
type hold_state_type is ( hold_release_state, hold_request_state );
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Signals
|
-- Signals
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
signal rst_n : Std_logic; -- Master Reset input (active low)
|
|
signal nmi_n : Std_logic; -- Non Maskable Interrupt input (active low)
|
|
|
|
-- BOOT ROM
|
-- BOOT ROM
|
signal rom_cs : Std_logic;
|
signal rom_cs : Std_logic;
|
signal rom_data_out : Std_Logic_Vector(7 downto 0);
|
signal rom_data_out : Std_Logic_Vector(7 downto 0);
|
|
|
-- Flex Memory & Monitor Stack
|
-- Flex Memory & Monitor Stack
|
| Line 255... |
Line 285... |
signal keyboard_irq : std_logic;
|
signal keyboard_irq : std_logic;
|
|
|
-- RAM
|
-- RAM
|
signal ram_cs : std_logic; -- memory chip select
|
signal ram_cs : std_logic; -- memory chip select
|
signal ram_data_out : std_logic_vector(7 downto 0);
|
signal ram_data_out : std_logic_vector(7 downto 0);
|
|
signal ram_rd_req : std_logic; -- ram read request (asynch set on ram read, cleared falling CPU clock edge)
|
|
signal ram_wr_req : std_logic; -- ram write request (set on rising CPU clock edge, asynch clear on acknowledge)
|
signal ram_hold : std_logic; -- hold off slow accesses
|
signal ram_hold : std_logic; -- hold off slow accesses
|
|
signal ram_release : std_logic; -- Release ram hold
|
|
|
-- CPU Interface signals
|
-- CPU Interface signals
|
signal cpu_reset : Std_Logic;
|
signal cpu_reset : Std_Logic;
|
signal cpu_clk : Std_Logic;
|
signal cpu_clk : Std_Logic;
|
signal cpu_rw : std_logic;
|
signal cpu_rw : std_logic;
|
| Line 312... |
Line 345... |
signal ide_cs : std_logic; -- IDE CF interface
|
signal ide_cs : std_logic; -- IDE CF interface
|
signal ether_cs : std_logic; -- Ethernet interface
|
signal ether_cs : std_logic; -- Ethernet interface
|
signal slot1_cs : std_logic; -- Expansion slot 1
|
signal slot1_cs : std_logic; -- Expansion slot 1
|
signal slot2_cs : std_logic; -- Expansion slot 2
|
signal slot2_cs : std_logic; -- Expansion slot 2
|
|
|
|
|
-- SDRAM
|
|
|
|
constant FREQ : natural := 100_000; -- operating frequency in KHz
|
|
constant CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
|
|
constant PIPE_EN : boolean := false; -- if true, enable pipelined read operations
|
|
constant MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh
|
|
constant MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank
|
|
constant DATA_WIDTH : natural := 16; -- host & SDRAM data width
|
|
constant NROWS : natural := 8192; -- number of rows in SDRAM array
|
|
constant NCOLS : natural := 512; -- number of columns in SDRAM array
|
|
constant HADDR_WIDTH : natural := 24; -- host-side address width
|
|
constant SADDR_WIDTH : natural := 13; -- SDRAM-side address width
|
|
|
|
signal rst_i : std_logic; -- internal reset signal
|
signal rst_i : std_logic; -- internal reset signal
|
signal clk_i : std_logic; -- internal master clock signal
|
signal clk_i : std_logic; -- internal master clock signal
|
signal lock : std_logic; -- SDRAM clock DLL lock indicator
|
signal lock : std_logic; -- SDRAM clock DLL lock indicator
|
|
|
-- signals that go through the SDRAM host-side interface
|
-- signals that go through the SDRAM host-side interface
|
| Line 341... |
Line 360... |
signal hAddr : std_logic_vector(HADDR_WIDTH-1 downto 0); -- host address bus
|
signal hAddr : std_logic_vector(HADDR_WIDTH-1 downto 0); -- host address bus
|
signal hDIn : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data to SDRAM
|
signal hDIn : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data to SDRAM
|
signal hDOut : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data from SDRAM
|
signal hDOut : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data from SDRAM
|
signal hRd : std_logic; -- host-side read control signal
|
signal hRd : std_logic; -- host-side read control signal
|
signal hWr : std_logic; -- host-side write control signal
|
signal hWr : std_logic; -- host-side write control signal
|
|
signal hUds : std_logic; -- host-side upper data strobe
|
|
signal hLds : std_logic; -- host-side lower data strobe
|
signal rdPending : std_logic; -- read operation pending in SDRAM pipeline
|
signal rdPending : std_logic; -- read operation pending in SDRAM pipeline
|
type ram_rd_type is (rd_state0, rd_state1, rd_state2, rd_state3);
|
type ram_type is (ram_state_0,
|
type ram_wr_type is (wr_state0, wr_state1, wr_state2, wr_state3, wr_state4);
|
ram_state_rd1, ram_state_rd2,
|
signal ram_rd_state : ram_rd_type;
|
ram_state_wr1,
|
signal ram_wr_state : ram_wr_type;
|
ram_state_3 );
|
|
signal ram_state : ram_type;
|
|
|
|
|
-- signal BaudCount : std_logic_vector(5 downto 0);
|
-- signal BaudCount : std_logic_vector(5 downto 0);
|
signal CountL : std_logic_vector(23 downto 0);
|
signal CountL : std_logic_vector(23 downto 0);
|
signal clk_count : std_logic_vector(0 downto 0);
|
signal clk_count : natural range 0 to CPU_CLK_DIV;
|
signal Clk25 : std_logic;
|
signal Clk25 : std_logic;
|
signal pix_clk : std_logic;
|
signal vga_clk : std_logic;
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
-- CPU09 CPU core
|
-- CPU09 CPU core
|
--
|
--
|
| Line 447... |
Line 470... |
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
|
|
component ACIA_Clock
|
component ACIA_Clock
|
generic (
|
generic (
|
SYS_CLK_FREQ : integer := SYS_Clock_Frequency;
|
SYS_CLK_FREQ : integer := SYS_CLK_FREQ;
|
ACIA_CLK_FREQ : integer := ACIA_Clock_Frequency
|
ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
|
);
|
);
|
port (
|
port (
|
clk : in Std_Logic; -- System Clock Input
|
clk : in Std_Logic; -- System Clock Input
|
acia_clk : out Std_logic -- ACIA Clock output
|
ACIA_clk : out Std_logic -- ACIA Clock output
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
| Line 465... |
Line 488... |
--
|
--
|
----------------------------------------
|
----------------------------------------
|
|
|
component keyboard
|
component keyboard
|
generic(
|
generic(
|
KBD_CLK_FREQ : integer := CPU_Clock_Frequency
|
KBD_CLK_FREQ : integer := CPU_CLK_FREQ
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
| Line 488... |
Line 511... |
-- Video Display Unit.
|
-- Video Display Unit.
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
component vdu8
|
component vdu8
|
generic(
|
generic(
|
VDU_CLOCK_FREQUENCY : integer := CPU_Clock_Frequency; -- HZ
|
VDU_CLK_FREQ : integer := CPU_CLK_FREQ; -- HZ
|
VGA_CLOCK_FREQUENCY : integer := PIX_Clock_Frequency; -- HZ
|
VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- HZ
|
VGA_HOR_CHARS : integer := 80; -- CHARACTERS
|
VGA_HOR_CHARS : integer := 80; -- CHARACTERS
|
VGA_VER_CHARS : integer := 25; -- CHARACTERS
|
VGA_VER_CHARS : integer := 25; -- CHARACTERS
|
VGA_PIXELS_PER_CHAR : integer := 8; -- PIXELS
|
VGA_PIX_PER_CHAR : integer := 8; -- PIXELS
|
VGA_LINES_PER_CHAR : integer := 16; -- LINES
|
VGA_LIN_PER_CHAR : integer := 16; -- LINES
|
VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
|
VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
|
VGA_HOR_SYNC : integer := 96; -- PIXELS
|
VGA_HOR_SYNC : integer := 96; -- PIXELS
|
VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
|
VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
|
VGA_VER_BACK_PORCH : integer := 13; -- LINES
|
VGA_VER_BACK_PORCH : integer := 13; -- LINES
|
VGA_VER_SYNC : integer := 1; -- LINES
|
VGA_VER_SYNC : integer := 2; -- LINES
|
VGA_VER_FRONT_PORCH : integer := 36 -- LINES
|
VGA_VER_FRONT_PORCH : integer := 35 -- LINES
|
);
|
);
|
port(
|
port(
|
-- control register interface
|
-- control register interface
|
vdu_clk : in std_logic; -- CPU Clock - 25MHz
|
vdu_clk : in std_logic; -- CPU Clock - 25MHz
|
vdu_rst : in std_logic;
|
vdu_rst : in std_logic;
|
| Line 580... |
Line 603... |
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0)
|
data_out : out std_logic_vector(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
component XSASDRAMCntl
|
component XSASDRAMCntl
|
generic(
|
generic(
|
FREQ : natural := FREQ; -- operating frequency in KHz
|
FREQ : natural := MEM_CLK_FREQ;-- operating frequency in KHz
|
CLK_DIV : real := CLK_DIV; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
|
CLK_DIV : real := SYS_CLK_DIV; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
|
PIPE_EN : boolean := PIPE_EN; -- if true, enable pipelined read operations
|
PIPE_EN : boolean := PIPE_EN; -- if true, enable pipelined read operations
|
MAX_NOP : natural := MAX_NOP; -- number of NOPs before entering self-refresh
|
MAX_NOP : natural := MAX_NOP; -- number of NOPs before entering self-refresh
|
MULTIPLE_ACTIVE_ROWS : boolean := MULTIPLE_ACTIVE_ROWS; -- if true, allow an active row in each bank
|
MULTIPLE_ACTIVE_ROWS : boolean := MULTIPLE_ACTIVE_ROWS; -- if true, allow an active row in each bank
|
DATA_WIDTH : natural := DATA_WIDTH; -- host & SDRAM data width
|
DATA_WIDTH : natural := DATA_WIDTH; -- host & SDRAM data width
|
NROWS : natural := NROWS; -- number of rows in SDRAM array
|
NROWS : natural := NROWS; -- number of rows in SDRAM array
|
| Line 603... |
Line 627... |
clk2x : out std_logic; -- double-speed host clock
|
clk2x : out std_logic; -- double-speed host clock
|
lock : out std_logic; -- true when host clock is locked to master clock
|
lock : out std_logic; -- true when host clock is locked to master clock
|
rst : in std_logic; -- reset
|
rst : in std_logic; -- reset
|
rd : in std_logic; -- initiate read operation
|
rd : in std_logic; -- initiate read operation
|
wr : in std_logic; -- initiate write operation
|
wr : in std_logic; -- initiate write operation
|
|
uds : in std_logic; -- upper data strobe
|
|
lds : in std_logic; -- lower data strobe
|
earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async)
|
earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async)
|
opBegun : out std_logic; -- read/write/self-refresh op begun (clocked)
|
opBegun : out std_logic; -- read/write/self-refresh op begun (clocked)
|
rdPending : out std_logic; -- read operation(s) are still in the pipeline
|
rdPending : out std_logic; -- read operation(s) are still in the pipeline
|
done : out std_logic; -- read or write operation is done
|
done : out std_logic; -- read or write operation is done
|
rdDone : out std_logic; -- read done and data is available
|
rdDone : out std_logic; -- read done and data is available
|
| Line 688... |
Line 714... |
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(0),
|
addr => cpu_addr(0),
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => acia_data_out,
|
data_out => acia_data_out,
|
irq => acia_irq,
|
irq => acia_irq,
|
|
|
RxC => acia_clk,
|
RxC => acia_clk,
|
TxC => acia_clk,
|
TxC => acia_clk,
|
RxD => rxd,
|
RxD => rxd,
|
TxD => txd,
|
TxD => txd,
|
DCD_n => dcd_n,
|
DCD_n => dcd_n,
|
| Line 701... |
Line 726... |
);
|
);
|
|
|
|
|
my_ACIA_Clock : ACIA_Clock
|
my_ACIA_Clock : ACIA_Clock
|
generic map(
|
generic map(
|
SYS_CLK_FREQ => SYS_Clock_Frequency,
|
SYS_CLK_FREQ => SYS_CLK_FREQ,
|
ACIA_CLK_FREQ => ACIA_Clock_Frequency
|
ACIA_CLK_FREQ => ACIA_CLK_FREQ
|
)
|
)
|
port map(
|
port map(
|
clk => Clk_i,
|
clk => Clk_i,
|
acia_clk => acia_clk
|
acia_clk => acia_clk
|
);
|
);
|
| Line 716... |
Line 741... |
-- PS/2 Keyboard Interface
|
-- PS/2 Keyboard Interface
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_keyboard : keyboard
|
my_keyboard : keyboard
|
generic map (
|
generic map (
|
KBD_CLK_FREQ => CPU_Clock_frequency
|
KBD_CLK_FREQ => CPU_CLK_FREQ
|
)
|
)
|
port map(
|
port map(
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => keyboard_cs,
|
cs => keyboard_cs,
|
| Line 738... |
Line 763... |
-- Video Display Unit instantiation
|
-- Video Display Unit instantiation
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_vdu : vdu8
|
my_vdu : vdu8
|
generic map(
|
generic map(
|
VDU_CLOCK_FREQUENCY => CPU_Clock_Frequency, -- HZ
|
VDU_CLK_FREQ => CPU_CLK_FREQ, -- HZ
|
VGA_CLOCK_FREQUENCY => PIX_Clock_Frequency, -- HZ
|
VGA_CLK_FREQ => VGA_CLK_FREQ, -- HZ
|
VGA_HOR_CHARS => 80, -- CHARACTERS
|
VGA_HOR_CHARS => 80, -- CHARACTERS
|
VGA_VER_CHARS => 25, -- CHARACTERS
|
VGA_VER_CHARS => 25, -- CHARACTERS
|
VGA_PIXELS_PER_CHAR => 8, -- PIXELS
|
VGA_PIX_PER_CHAR => 8, -- PIXELS
|
VGA_LINES_PER_CHAR => 16, -- LINES
|
VGA_LIN_PER_CHAR => 16, -- LINES
|
VGA_HOR_BACK_PORCH => 40, -- PIXELS
|
VGA_HOR_BACK_PORCH => 40, -- PIXELS
|
VGA_HOR_SYNC => 96, -- PIXELS
|
VGA_HOR_SYNC => 96, -- PIXELS
|
VGA_HOR_FRONT_PORCH => 24, -- PIXELS
|
VGA_HOR_FRONT_PORCH => 24, -- PIXELS
|
VGA_VER_BACK_PORCH => 13, -- LINES
|
VGA_VER_BACK_PORCH => 13, -- LINES
|
VGA_VER_SYNC => 1, -- LINES
|
VGA_VER_SYNC => 2, -- LINES
|
VGA_VER_FRONT_PORCH => 36 -- LINES
|
VGA_VER_FRONT_PORCH => 35 -- LINES
|
)
|
)
|
port map(
|
port map(
|
|
|
-- Control Registers
|
-- Control Registers
|
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
|
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
|
| Line 763... |
Line 788... |
vdu_addr => cpu_addr(2 downto 0),
|
vdu_addr => cpu_addr(2 downto 0),
|
vdu_data_in => cpu_data_out,
|
vdu_data_in => cpu_data_out,
|
vdu_data_out => vdu_data_out,
|
vdu_data_out => vdu_data_out,
|
|
|
-- vga port connections
|
-- vga port connections
|
vga_clk => pix_clk, -- 25 MHz VDU pixel clock
|
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
|
vga_red_o => vga_red_o,
|
vga_red_o => vga_red_o,
|
vga_green_o => vga_green_o,
|
vga_green_o => vga_green_o,
|
vga_blue_o => vga_blue_o,
|
vga_blue_o => vga_blue_o,
|
vga_hsync_o => vga_hsync_n,
|
vga_hsync_o => vga_hsync_n,
|
vga_vsync_o => vga_vsync_n
|
vga_vsync_o => vga_vsync_n
|
| Line 822... |
Line 847... |
-- Instantiate the SDRAM controller that connects to the memory tester
|
-- Instantiate the SDRAM controller that connects to the memory tester
|
-- module and interfaces to the external SDRAM chip.
|
-- module and interfaces to the external SDRAM chip.
|
------------------------------------------------------------------------
|
------------------------------------------------------------------------
|
u1 : xsaSDRAMCntl
|
u1 : xsaSDRAMCntl
|
generic map(
|
generic map(
|
FREQ => FREQ,
|
FREQ => MEM_CLK_FREQ,
|
|
CLK_DIV => SYS_CLK_DIV,
|
PIPE_EN => PIPE_EN,
|
PIPE_EN => PIPE_EN,
|
DATA_WIDTH => DATA_WIDTH,
|
MAX_NOP => MAX_NOP,
|
MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS,
|
MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS,
|
|
DATA_WIDTH => DATA_WIDTH,
|
NROWS => NROWS,
|
NROWS => NROWS,
|
NCOLS => NCOLS,
|
NCOLS => NCOLS,
|
HADDR_WIDTH => HADDR_WIDTH,
|
HADDR_WIDTH => HADDR_WIDTH,
|
SADDR_WIDTH => SADDR_WIDTH
|
SADDR_WIDTH => SADDR_WIDTH
|
)
|
)
|
| Line 841... |
Line 868... |
clk2x => open, -- synchronized doubled master clock
|
clk2x => open, -- synchronized doubled master clock
|
lock => lock, -- DLL lock indicator
|
lock => lock, -- DLL lock indicator
|
rst => rst_i, -- reset
|
rst => rst_i, -- reset
|
rd => hRd, -- host-side SDRAM read control from memory tester
|
rd => hRd, -- host-side SDRAM read control from memory tester
|
wr => hWr, -- host-side SDRAM write control from memory tester
|
wr => hWr, -- host-side SDRAM write control from memory tester
|
|
uds => hUds, -- host-side SDRAM upper data strobe
|
|
lds => hLds, -- host-side SDRAM lower data strobe
|
rdPending => rdPending,-- read operation to SDRAM is in progress
|
rdPending => rdPending,-- read operation to SDRAM is in progress
|
opBegun => opBegun, -- indicates memory read/write has begun
|
opBegun => opBegun, -- indicates memory read/write has begun
|
earlyOpBegun => earlyBegun, -- early indicator that memory operation has begun
|
earlyOpBegun => earlyBegun, -- early indicator that memory operation has begun
|
rdDone => rdDone, -- indicates SDRAM memory read operation is done
|
rdDone => rdDone, -- indicates SDRAM memory read operation is done
|
done => ramDone, -- indicates SDRAM memory read or write operation is done
|
done => ramDone, -- indicates SDRAM memory read or write operation is done
|
| Line 870... |
Line 899... |
cpu_clk_buffer : BUFG port map(
|
cpu_clk_buffer : BUFG port map(
|
i => Clk25,
|
i => Clk25,
|
o => cpu_clk
|
o => cpu_clk
|
);
|
);
|
|
|
pix_clk_buffer : BUFG port map(
|
vga_clk_buffer : BUFG port map(
|
i => Clk25,
|
i => Clk25,
|
o => pix_clk
|
o => vga_clk
|
);
|
);
|
|
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
--
|
--
|
-- Process to decode memory map
|
-- Process to decode memory map
|
--
|
--
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
|
|
mem_decode: process( cpu_clk,
|
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
|
cpu_addr, cpu_rw, cpu_vma,
|
|
dat_addr,
|
dat_addr,
|
rom_data_out,
|
rom_data_out,
|
flex_data_out,
|
flex_data_out,
|
acia_data_out,
|
acia_data_out,
|
keyboard_data_out,
|
keyboard_data_out,
|
| Line 1055... |
Line 1083... |
-- 16-bit Peripheral Bus
|
-- 16-bit Peripheral Bus
|
-- 6809 Big endian
|
-- 6809 Big endian
|
-- ISA bus little endian
|
-- ISA bus little endian
|
-- Not sure about IDE interface
|
-- Not sure about IDE interface
|
--
|
--
|
peripheral_bus: process( clk_i, cpu_reset, cpu_rw, cpu_addr, cpu_data_out )
|
peripheral_bus: process( clk_i, cpu_reset, cpu_rw, cpu_addr, cpu_data_out,
|
|
pb_cs, pb_wreg, pb_rreg )
|
begin
|
begin
|
pb_wru <= pb_cs and (not cpu_rw) and (not cpu_addr(0));
|
pb_wru <= pb_cs and (not cpu_rw) and (not cpu_addr(0));
|
pb_wrl <= pb_cs and (not cpu_rw) and cpu_addr(0) ;
|
pb_wrl <= pb_cs and (not cpu_rw) and cpu_addr(0) ;
|
pb_rdu <= pb_cs and cpu_rw and (not cpu_addr(0));
|
pb_rdu <= pb_cs and cpu_rw and (not cpu_addr(0));
|
pb_rdl <= pb_cs and cpu_rw and cpu_addr(0) ;
|
pb_rdl <= pb_cs and cpu_rw and cpu_addr(0) ;
|
| Line 1126... |
Line 1155... |
end process;
|
end process;
|
|
|
--
|
--
|
-- Hold Peripheral bus accesses for a few cycles
|
-- Hold Peripheral bus accesses for a few cycles
|
--
|
--
|
peripheral_bus_hold: process( cpu_clk, cpu_reset, pb_rdu, pb_wrl, ether_rdy )
|
peripheral_bus_hold: process( cpu_clk, cpu_reset, pb_rdu, pb_wrl ) --, ether_rdy )
|
begin
|
begin
|
if cpu_reset = '1' then
|
if cpu_reset = '1' then
|
pb_release <= '0';
|
pb_release <= '0';
|
pb_count <= "0000";
|
pb_count <= "0000";
|
pb_hold_state <= hold_release_state;
|
pb_hold_state <= hold_release_state;
|
elsif cpu_clk'event and cpu_clk='1' then
|
elsif rising_edge(cpu_clk) then
|
--
|
--
|
-- The perpheral bus hold signal should be generated on
|
-- The perpheral bus hold signal should be generated on
|
-- 16 bit bus read which will be on even byte reads or
|
-- 16 bit bus read which will be on even byte reads or
|
-- 16 bit bus write which will be on odd byte writes.
|
-- 16 bit bus write which will be on odd byte writes.
|
--
|
--
|
| Line 1151... |
Line 1180... |
pb_hold_state <= hold_release_state;
|
pb_hold_state <= hold_release_state;
|
end if;
|
end if;
|
|
|
when hold_request_state =>
|
when hold_request_state =>
|
if pb_count = "0000" then
|
if pb_count = "0000" then
|
if ether_rdy = '1' then
|
-- if ether_rdy = '1' then
|
pb_release <= '1';
|
pb_release <= '1';
|
pb_hold_state <= hold_release_state;
|
pb_hold_state <= hold_release_state;
|
end if;
|
-- end if;
|
else
|
else
|
pb_count <= pb_count - "0001";
|
pb_count <= pb_count - "0001";
|
end if;
|
end if;
|
when others =>
|
when others =>
|
null;
|
null;
|
| Line 1177... |
Line 1206... |
end process;
|
end process;
|
|
|
--
|
--
|
-- Interrupts and other bus control signals
|
-- Interrupts and other bus control signals
|
--
|
--
|
interrupts : process( lock, rst_n, nmi_n,
|
interrupts : process( SW3_N,
|
pb_cs, pb_hold, pb_release,
|
pb_cs, pb_hold, pb_release, ram_hold,
|
ram_cs, ram_hold,
|
-- ether_irq,
|
ether_irq,
|
|
acia_irq,
|
acia_irq,
|
keyboard_irq,
|
keyboard_irq,
|
trap_irq,
|
trap_irq,
|
timer_irq
|
timer_irq
|
)
|
)
|
begin
|
begin
|
cpu_reset <= (not rst_n) or (not lock); -- CPU reset is active high
|
|
pb_hold <= pb_cs and (not pb_release);
|
pb_hold <= pb_cs and (not pb_release);
|
cpu_irq <= acia_irq or keyboard_irq;
|
cpu_irq <= acia_irq or keyboard_irq;
|
cpu_nmi <= trap_irq or not( nmi_n );
|
cpu_nmi <= trap_irq or not( SW3_N );
|
cpu_firq <= timer_irq;
|
cpu_firq <= timer_irq;
|
cpu_halt <= '0';
|
cpu_halt <= '0';
|
cpu_hold <= pb_hold or ram_hold;
|
cpu_hold <= pb_hold or ram_hold;
|
|
FLASH_CE_N <= '1';
|
end process;
|
end process;
|
|
|
|
|
--
|
--
|
-- Flash 7 segment LEDS
|
-- Flash 7 segment LEDS
|
--
|
--
|
my_led_flasher: process( Clk_i, rst_n, CountL )
|
my_led_flasher: process( clk_i, rst_i, CountL )
|
begin
|
begin
|
if rst_n = '0' then
|
if rst_i = '1' then
|
CountL <= "000000000000000000000000";
|
CountL <= "000000000000000000000000";
|
elsif(Clk_i'event and Clk_i = '1') then
|
elsif rising_edge(clk_i) then
|
CountL <= CountL + 1;
|
CountL <= CountL + 1;
|
end if;
|
end if;
|
-- S(7 downto 0) <= CountL(23 downto 16);
|
-- S(7 downto 0) <= CountL(23 downto 16);
|
end process;
|
end process;
|
|
|
--
|
--
|
-- Generate a 25 MHz Clock from 50 MHz
|
-- Generate CPU & Pixel Clock from Memory Clock
|
--
|
--
|
my_prescaler : process( Clk_i, clk_count )
|
my_prescaler : process( clk_i, clk_count )
|
begin
|
begin
|
if Clk_i'event and Clk_i = '1' then
|
if rising_edge( clk_i ) then
|
clk_count(0) <= not clk_count(0);
|
|
|
if clk_count = 0 then
|
|
clk_count <= CPU_CLK_DIV-1;
|
|
else
|
|
clk_count <= clk_count - 1;
|
|
end if;
|
|
|
|
if clk_count = 0 then
|
|
clk25 <= '0';
|
|
elsif clk_count = (CPU_CLK_DIV/2) then
|
|
clk25 <= '1';
|
|
end if;
|
|
|
end if;
|
end if;
|
Clk25 <= clk_count(0);
|
|
end process;
|
end process;
|
|
|
--
|
--
|
-- Push buttons
|
-- Reset button and reset timer
|
--
|
--
|
my_switch_assignments : process( SW2_N, SW3_N, rst_n )
|
my_switch_assignments : process( rst_i, SW2_N, lock )
|
begin
|
begin
|
rst_n <= SW2_N;
|
rst_i <= not SW2_N;
|
rst_i <= not rst_n;
|
cpu_reset <= rst_i or (not lock);
|
nmi_n <= SW3_N;
|
|
--
|
|
-- Disable Flash memory
|
|
--
|
|
FLASH_CE_N <= '1';
|
|
end process;
|
end process;
|
|
|
--
|
--
|
-- RS232 signals:
|
-- RS232 signals:
|
--
|
--
|
| Line 1283... |
Line 1317... |
VGA_blue(1) <= vga_blue_o;
|
VGA_blue(1) <= vga_blue_o;
|
VGA_blue(2) <= vga_blue_o;
|
VGA_blue(2) <= vga_blue_o;
|
end process;
|
end process;
|
|
|
--
|
--
|
-- SDRAM assignments
|
-- SDRAM read write control
|
--
|
--
|
my_sdram_assignments : process( cpu_clk, clk_i, cpu_reset,
|
my_sdram_rw : process( clk_i, cpu_reset,
|
opBegun, rdDone, wrDone,
|
opBegun, ramDone,
|
ram_rd_state, ram_wr_state,
|
ram_state,
|
cpu_addr, dat_addr,
|
ram_rd_req, ram_wr_req )
|
cpu_data_out, hDout,
|
|
ram_cs, cpu_rw, ram_hold )
|
|
begin
|
begin
|
if( cpu_reset = '1' ) then
|
if( cpu_reset = '1' ) then
|
hWr <= '0';
|
|
hRd <= '0';
|
hRd <= '0';
|
wrDone <= '0';
|
hWr <= '0';
|
ram_wr_state <= wr_state0;
|
ram_hold <= '0';
|
ram_rd_state <= rd_state0;
|
ram_state <= ram_state_0;
|
|
|
elsif( clk_i'event and clk_i='0' ) then
|
elsif( falling_edge(clk_i) ) then
|
--
|
--
|
-- read state machine
|
-- ram state machine
|
--
|
--
|
case ram_rd_state is
|
case ram_state is
|
|
|
when rd_state0 =>
|
when ram_state_0 =>
|
if (ram_hold = '1') and (cpu_rw = '1') then
|
if ram_rd_req = '1' then
|
|
ram_hold <= '1';
|
hRd <= '1';
|
hRd <= '1';
|
ram_rd_state <= rd_state1;
|
ram_state <= ram_state_rd1;
|
|
elsif ram_wr_req = '1' then
|
|
ram_hold <= '1';
|
|
hWr <= '1';
|
|
ram_state <= ram_state_wr1;
|
end if;
|
end if;
|
|
|
when rd_state1 =>
|
when ram_state_rd1 =>
|
if opBegun = '1' then
|
if opBegun = '1' then
|
ram_rd_state <= rd_state2;
|
hRd <= '0';
|
|
ram_state <= ram_state_rd2;
|
end if;
|
end if;
|
|
|
when rd_state2 =>
|
when ram_state_rd2 =>
|
if rdDone = '1' then
|
if ramDone = '1' then
|
hRd <= '0';
|
ram_hold <= '0';
|
ram_rd_state <= rd_state3;
|
ram_state <= ram_state_3;
|
end if;
|
end if;
|
|
|
when rd_state3 =>
|
when ram_state_wr1 =>
|
if rdDone = '0' then
|
if opBegun = '1' then
|
ram_rd_state <= rd_state0;
|
ram_hold <= '0';
|
|
hWr <= '0';
|
|
ram_state <= ram_state_3;
|
|
end if;
|
|
|
|
when ram_state_3 =>
|
|
if ram_release = '1' then
|
|
ram_state <= ram_state_0;
|
end if;
|
end if;
|
|
|
when others =>
|
when others =>
|
hRd <= '0';
|
hRd <= '0';
|
ram_rd_state <= rd_state0;
|
hWr <= '0';
|
|
ram_hold <= '0';
|
|
ram_state <= ram_state_0;
|
end case;
|
end case;
|
|
|
|
end if;
|
|
end process;
|
|
|
--
|
--
|
-- Write state machine
|
-- SDRAM Address and data bus assignments
|
--
|
--
|
case ram_wr_state is
|
my_sdram_addr_data : process( cpu_addr, dat_addr,
|
|
cpu_data_out, hDout )
|
when wr_state0 =>
|
begin
|
if (ram_hold = '1') and (cpu_rw = '0') then
|
hAddr(23 downto 19) <= "00000";
|
hWr <= '1';
|
hAddr(18 downto 11) <= dat_addr;
|
wrDone <= '0';
|
hAddr(10 downto 0) <= cpu_addr(11 downto 1);
|
ram_wr_state <= wr_state1;
|
hUds <= not cpu_addr(0);
|
|
hLds <= cpu_addr(0);
|
|
if cpu_addr(0) = '0' then
|
|
hDin( 7 downto 0) <= (others=>'0');
|
|
hDin(15 downto 8) <= cpu_data_out;
|
|
ram_data_out <= hDout(15 downto 8);
|
|
else
|
|
hDin( 7 downto 0) <= cpu_data_out;
|
|
hDin(15 downto 8) <= (others=>'0');
|
|
ram_data_out <= hDout( 7 downto 0);
|
end if;
|
end if;
|
|
end process;
|
|
|
when wr_state1 =>
|
--
|
if opBegun = '1' then
|
-- Hold RAM until falling CPU clock edge
|
hWr <= '0';
|
--
|
wrDone <= '0';
|
ram_bus_hold: process( cpu_clk, cpu_reset, ram_hold )
|
ram_wr_state <= wr_state2;
|
begin
|
|
if ram_hold = '1' then
|
|
ram_release <= '0';
|
|
elsif falling_edge(cpu_clk) then
|
|
ram_release <= '1';
|
end if;
|
end if;
|
|
end process;
|
|
|
when wr_state2 =>
|
|
hWr <= '0';
|
|
wrDone <= '0';
|
|
ram_wr_state <= wr_state3;
|
|
|
|
when wr_state3 =>
|
|
hWr <= '0';
|
|
wrDone <= '1';
|
|
ram_wr_state <= wr_state4;
|
|
|
|
when wr_state4 =>
|
|
hWr <= '0';
|
|
wrDone <= '0';
|
|
ram_wr_state <= wr_state0;
|
|
|
|
when others =>
|
|
hWr <= '0';
|
|
wrDone <= '0';
|
|
ram_wr_state <= wr_state0;
|
|
|
|
end case;
|
|
|
|
end if;
|
|
--
|
--
|
-- Strobe host RD and WR signals high on RAM select
|
-- CPU read data request on rising CPU clock edge
|
-- Return low when cycle has started
|
|
--
|
--
|
if( cpu_reset = '1' ) then
|
ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release )
|
ram_hold <= '0';
|
begin
|
elsif( cpu_clk'event and cpu_clk='1' ) then
|
if hRd = '1' then
|
|
ram_rd_req <= '0';
|
|
elsif rising_edge(cpu_clk) then
|
|
if (ram_cs = '1') and (cpu_rw = '1') and (ram_release = '1') then
|
|
ram_rd_req <= '1';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
--
|
--
|
-- Hold is intitiated when the RAM is selected
|
-- CPU write data to RAM valid on rising CPU clock edge
|
-- and released when access cycle is complete
|
|
--
|
--
|
if (ram_hold = '0') and (ram_cs = '1') then
|
ram_write_request: process( hWr, cpu_clk, ram_cs, cpu_rw, ram_release )
|
ram_hold <= '1';
|
begin
|
elsif (ram_hold = '1') and ((rdDone = '1') or (wrDone = '1')) then
|
if hWr = '1' then
|
ram_hold <= '0';
|
ram_wr_req <= '0';
|
|
elsif rising_edge(cpu_clk) then
|
|
if (ram_cs = '1') and (cpu_rw = '0') and (ram_release = '1') then
|
|
ram_wr_req <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
end process;
|
|
|
|
|
hAddr(23 downto 20) <= "0000";
|
|
hAddr(19 downto 12) <= dat_addr;
|
|
hAddr(11 downto 0) <= cpu_addr(11 downto 0);
|
|
hDin(7 downto 0) <= cpu_data_out;
|
|
hDin(15 downto 8) <= (others => '0');
|
|
ram_data_out <= hDout(7 downto 0);
|
|
|
|
|
status_leds : process( rst_i, cpu_reset, lock )
|
|
begin
|
|
S(0) <= rst_i;
|
|
S(1) <= cpu_reset;
|
|
S(2) <= lock;
|
|
S(3) <= countL(23);
|
|
S(7 downto 4) <= "0000";
|
end process;
|
end process;
|
|
|
|
--debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
|
|
-- cpu_halt, cpu_hold,
|
|
-- cpu_firq, cpu_irq, cpu_nmi,
|
|
-- cpu_addr, cpu_data_out, cpu_data_in )
|
|
--begin
|
|
-- cpu_reset_o <= cpu_reset;
|
|
-- cpu_clk_o <= cpu_clk;
|
|
-- cpu_rw_o <= cpu_rw;
|
|
-- cpu_vma_o <= cpu_vma;
|
|
-- cpu_halt_o <= cpu_halt;
|
|
-- cpu_hold_o <= cpu_hold;
|
|
-- cpu_firq_o <= cpu_firq;
|
|
-- cpu_irq_o <= cpu_irq;
|
|
-- cpu_nmi_o <= cpu_nmi;
|
|
-- cpu_addr_o <= cpu_addr;
|
|
-- cpu_data_out_o <= cpu_data_out;
|
|
-- cpu_data_in_o <= cpu_data_in;
|
|
--end process;
|
|
|
|
|
end rtl; --===================== End of architecture =======================--
|
end rtl; --===================== End of architecture =======================--
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
