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[/] [System09/] [trunk/] [rtl/] [System09_Xess_XSA-3S1000/] [System09_Xess_XSA-3S1000.vhd] - Diff between revs 115 and 134

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Rev 115 Rev 134
Line 369... Line 369...
                    ram_state_rd1, ram_state_rd2,
                    ram_state_rd1, ram_state_rd2,
                    ram_state_wr1,
                    ram_state_wr1,
                                                  ram_state_3 );
                                                  ram_state_3 );
  signal ram_state     : ram_type;
  signal ram_state     : ram_type;
 
 
 
 
--  signal BaudCount   : std_logic_vector(5 downto 0);
 
  signal CountL        : std_logic_vector(23 downto 0);
  signal CountL        : std_logic_vector(23 downto 0);
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
  signal Clk25         : std_logic;
  signal Clk25         : std_logic;
  signal vga_clk       : std_logic;
  signal vga_clk       : std_logic;
 
 
Line 399... Line 397...
         halt:     in  std_logic;
         halt:     in  std_logic;
         hold:     in  std_logic
         hold:     in  std_logic
  );
  );
end component;
end component;
 
 
 
 
----------------------------------------
----------------------------------------
--
--
-- 4K Block RAM Monitor ROM
-- 4K Block RAM Monitor ROM
 
-- $F000 - $FFFF
--
--
----------------------------------------
----------------------------------------
 
 
component mon_rom
component mon_rom
    Port (
    Port (
       clk   : in  std_logic;
       clk   : in  std_logic;
                 rst   : in  std_logic;
                 rst   : in  std_logic;
                 cs    : in  std_logic;
                 cs    : in  std_logic;
Line 417... Line 416...
       data_out : out std_logic_vector (7 downto 0);
       data_out : out std_logic_vector (7 downto 0);
       data_in : in  std_logic_vector (7 downto 0)
       data_in : in  std_logic_vector (7 downto 0)
    );
    );
end component;
end component;
 
 
 
 
----------------------------------------
----------------------------------------
--
--
-- 8KBytes Block RAM for FLEX9
-- 8KBytes Block RAM for FLEX9
-- $C000 - $DFFF
-- $C000 - $DFFF
--
--
----------------------------------------
----------------------------------------
 
 
component flex_ram
component flex_ram
  Port (
  Port (
    clk      : in  std_logic;
    clk      : in  std_logic;
    rst      : in  std_logic;
    rst      : in  std_logic;
    cs       : in  std_logic;
    cs       : in  std_logic;
Line 458... Line 457...
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
     RxD      : in  Std_Logic;  -- Receive Data
     RxD      : in  Std_Logic;  -- Receive Data
     TxD      : out Std_Logic;  -- Transmit Data
     TxD      : out Std_Logic;  -- Transmit Data
     DCD_n    : in  Std_Logic;  -- Data Carrier Detect
     DCD_n    : in  Std_Logic;  -- Data Carrier Detect
     CTS_n    : in  Std_Logic;  -- Clear To Send
     CTS_n    : in  Std_Logic;  -- Clear To Send
     RTS_n    : out Std_Logic );  -- Request To send
    RTS_n    : out Std_Logic   -- Request To send
 
  );
end component;
end component;
 
 
 
 
-----------------------------------------------------------------
-----------------------------------------------------------------
--
--
-- ACIA Clock divider
-- ACIA Clock divider
--
--
-----------------------------------------------------------------
-----------------------------------------------------------------
Line 479... Line 478...
     clk      : in  Std_Logic;  -- System Clock Input
     clk      : in  Std_Logic;  -- System Clock Input
          ACIA_clk : out Std_logic   -- ACIA Clock output
          ACIA_clk : out Std_logic   -- ACIA Clock output
  );
  );
end component;
end component;
 
 
 
 
----------------------------------------
----------------------------------------
--
--
-- PS/2 Keyboard
-- PS/2 Keyboard
--
--
----------------------------------------
----------------------------------------
Line 509... Line 507...
----------------------------------------
----------------------------------------
--
--
-- Video Display Unit.
-- Video Display Unit.
--
--
----------------------------------------
----------------------------------------
 
 
component vdu8
component vdu8
      generic(
      generic(
        VDU_CLK_FREQ           : integer := CPU_CLK_FREQ; -- HZ
        VDU_CLK_FREQ           : integer := CPU_CLK_FREQ; -- HZ
        VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
        VGA_CLK_FREQ           : integer := VGA_CLK_FREQ; -- HZ
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
Line 544... Line 543...
      vga_hsync_o  : out std_logic;
      vga_hsync_o  : out std_logic;
      vga_vsync_o  : out std_logic
      vga_vsync_o  : out std_logic
   );
   );
end component;
end component;
 
 
 
 
----------------------------------------
----------------------------------------
--
--
-- Timer module
-- Timer module
--
--
----------------------------------------
----------------------------------------
Line 584... Line 582...
         data_out   : out std_logic_vector(7 downto 0);
         data_out   : out std_logic_vector(7 downto 0);
         irq        : out std_logic
         irq        : out std_logic
  );
  );
end component;
end component;
 
 
 
 
----------------------------------------
----------------------------------------
--
--
-- Dynamic Address Translation Registers
-- Dynamic Address Translation Registers
--
--
----------------------------------------
----------------------------------------
 
 
component dat_ram
component dat_ram
  port (
  port (
    clk      : in  std_logic;
    clk      : in  std_logic;
         rst      : in  std_logic;
         rst      : in  std_logic;
         cs       : in  std_logic;
         cs       : in  std_logic;
Line 603... Line 601...
    data_in  : in  std_logic_vector(7 downto 0);
    data_in  : in  std_logic_vector(7 downto 0);
         data_out : out std_logic_vector(7 downto 0)
         data_out : out std_logic_vector(7 downto 0)
  );
  );
end component;
end component;
 
 
 
----------------------------------------
 
--
 
-- SDRAM Controller for XSA-3S1000
 
--
 
----------------------------------------
 
 
component XSASDRAMCntl
component XSASDRAMCntl
  generic(
  generic(
    FREQ                 :     natural := MEM_CLK_FREQ;-- operating frequency in KHz
    FREQ                 :     natural := MEM_CLK_FREQ;-- operating frequency in KHz
    CLK_DIV              :     real    := SYS_CLK_DIV; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
    CLK_DIV              :     real    := SYS_CLK_DIV; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
Line 658... Line 661...
end component;
end component;
 
 
--
--
-- Clock buffer
-- Clock buffer
--
--
 
 
component BUFG
component BUFG
   Port (
   Port (
     i: in std_logic;
     i: in std_logic;
          o: out std_logic
          o: out std_logic
  );
  );
end component;
end component;
 
 
begin
begin
 
 
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Instantiation of internal components
  -- Instantiation of internal components
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
 
 
my_cpu : cpu09  port map (
  my_cpu : cpu09
 
    port map (
         clk         => cpu_clk,
         clk         => cpu_clk,
    rst       => cpu_reset,
    rst       => cpu_reset,
    vma       => cpu_vma,
    vma       => cpu_vma,
    addr      => cpu_addr(15 downto 0),
    addr      => cpu_addr(15 downto 0),
    rw       => cpu_rw,
    rw       => cpu_rw,
Line 685... Line 691...
         nmi       => cpu_nmi,
         nmi       => cpu_nmi,
         halt      => cpu_halt,
         halt      => cpu_halt,
         hold      => cpu_hold
         hold      => cpu_hold
  );
  );
 
 
my_rom : mon_rom port map (
  my_rom : mon_rom
 
    port map (
       clk   => cpu_clk,
       clk   => cpu_clk,
                 rst   => cpu_reset,
                 rst   => cpu_reset,
                 cs    => rom_cs,
                 cs    => rom_cs,
                 rw    => '1',
                 rw    => '1',
       addr  => cpu_addr(11 downto 0),
       addr  => cpu_addr(11 downto 0),
       data_in => cpu_data_out,
       data_in => cpu_data_out,
       data_out => rom_data_out
       data_out => rom_data_out
    );
    );
 
 
my_flex : flex_ram port map (
  my_flex : flex_ram
 
    port map (
    clk       => cpu_clk,
    clk       => cpu_clk,
    rst       => cpu_reset,
    rst       => cpu_reset,
         cs        => flex_cs,
         cs        => flex_cs,
         rw        => cpu_rw,
         rw        => cpu_rw,
    addr      => cpu_addr(12 downto 0),
    addr      => cpu_addr(12 downto 0),
    data_out     => flex_data_out,
    data_out     => flex_data_out,
    data_in     => cpu_data_out
    data_in     => cpu_data_out
    );
    );
 
 
my_acia  : acia6850 port map (
  my_acia  : acia6850
 
    port map (
         clk         => cpu_clk,
         clk         => cpu_clk,
         rst       => cpu_reset,
         rst       => cpu_reset,
    cs        => acia_cs,
    cs        => acia_cs,
         rw        => cpu_rw,
         rw        => cpu_rw,
    addr      => cpu_addr(0),
    addr      => cpu_addr(0),
Line 723... Line 732...
         DCD_n     => dcd_n,
         DCD_n     => dcd_n,
         CTS_n     => cts_n,
         CTS_n     => cts_n,
         RTS_n     => rts_n
         RTS_n     => rts_n
         );
         );
 
 
 
 
my_ACIA_Clock : ACIA_Clock
my_ACIA_Clock : ACIA_Clock
  generic map(
  generic map(
    SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
    SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
         ACIA_CLK_FREQ => ACIA_CLK_FREQ
         ACIA_CLK_FREQ => ACIA_CLK_FREQ
  )
  )
Line 777... Line 785...
           VGA_VER_BACK_PORCH     => 13, -- LINES
           VGA_VER_BACK_PORCH     => 13, -- LINES
           VGA_VER_SYNC           => 2,  -- LINES
           VGA_VER_SYNC           => 2,  -- LINES
           VGA_VER_FRONT_PORCH    => 35  -- LINES
           VGA_VER_FRONT_PORCH    => 35  -- LINES
  )
  )
  port map(
  port map(
 
 
                -- Control Registers
                -- Control Registers
                vdu_clk       => cpu_clk,                                        -- 12.5 MHz System Clock in
                vdu_clk       => cpu_clk,                                        -- 12.5 MHz System Clock in
      vdu_rst       => cpu_reset,
      vdu_rst       => cpu_reset,
                vdu_cs        => vdu_cs,
                vdu_cs        => vdu_cs,
                vdu_rw        => cpu_rw,
                vdu_rw        => cpu_rw,
                vdu_addr      => cpu_addr(2 downto 0),
                vdu_addr      => cpu_addr(2 downto 0),
                vdu_data_in   => cpu_data_out,
                vdu_data_in   => cpu_data_out,
                vdu_data_out  => vdu_data_out,
                vdu_data_out  => vdu_data_out,
 
 
      -- vga port connections
      -- vga port connections
      vga_clk       => vga_clk,                                  -- 25 MHz VDU pixel clock
      vga_clk       => vga_clk,                                  -- 25 MHz VDU pixel clock
      vga_red_o     => vga_red_o,
      vga_red_o     => vga_red_o,
      vga_green_o   => vga_green_o,
      vga_green_o   => vga_green_o,
      vga_blue_o    => vga_blue_o,
      vga_blue_o    => vga_blue_o,
Line 801... Line 807...
----------------------------------------
----------------------------------------
--
--
-- Timer Module
-- Timer Module
--
--
----------------------------------------
----------------------------------------
my_timer  : timer port map (
  my_timer  : timer
 
    port map (
    clk       => cpu_clk,
    clk       => cpu_clk,
         rst       => cpu_reset,
         rst       => cpu_reset,
    cs        => timer_cs,
    cs        => timer_cs,
         rw        => cpu_rw,
         rw        => cpu_rw,
    addr      => cpu_addr(0),
    addr      => cpu_addr(0),
Line 817... Line 824...
----------------------------------------
----------------------------------------
--
--
-- Bus Trap Interrupt logic
-- Bus Trap Interrupt logic
--
--
----------------------------------------
----------------------------------------
my_trap : trap port map (
  my_trap : trap
 
    port map (
         clk        => cpu_clk,
         clk        => cpu_clk,
    rst        => cpu_reset,
    rst        => cpu_reset,
    cs         => trap_cs,
    cs         => trap_cs,
    rw         => cpu_rw,
    rw         => cpu_rw,
         vma        => cpu_vma,
         vma        => cpu_vma,
Line 829... Line 837...
    data_in    => cpu_data_out,
    data_in    => cpu_data_out,
         data_out   => trap_data_out,
         data_out   => trap_data_out,
         irq        => trap_irq
         irq        => trap_irq
    );
    );
 
 
 
  my_dat : dat_ram
my_dat : dat_ram port map (
    port map (
    clk       => cpu_clk,
    clk       => cpu_clk,
         rst       => cpu_reset,
         rst       => cpu_reset,
         cs        => dat_cs,
         cs        => dat_cs,
         rw        => cpu_rw,
         rw        => cpu_rw,
         addr_hi   => cpu_addr(15 downto 12),
         addr_hi   => cpu_addr(15 downto 12),
Line 894... Line 902...
      sData                => SDRAM_D,        -- SDRAM databus
      sData                => SDRAM_D,        -- SDRAM databus
      dqmh                 => SDRAM_dqmh,     -- SDRAM DQMH
      dqmh                 => SDRAM_dqmh,     -- SDRAM DQMH
      dqml                 => SDRAM_dqml      -- SDRAM DQML
      dqml                 => SDRAM_dqml      -- SDRAM DQML
      );
      );
 
 
cpu_clk_buffer : BUFG port map(
  cpu_clk_buffer : BUFG
 
    port map(
    i => Clk25,
    i => Clk25,
         o => cpu_clk
         o => cpu_clk
    );
    );
 
 
vga_clk_buffer : BUFG port map(
  vga_clk_buffer : BUFG
 
    port map(
    i => Clk25,
    i => Clk25,
         o => vga_clk
         o => vga_clk
    );
    );
 
 
----------------------------------------------------------------------
----------------------------------------------------------------------
Line 938... Line 948...
           ide_cs      <= '0';
           ide_cs      <= '0';
           ether_cs    <= '0';
           ether_cs    <= '0';
           slot1_cs    <= '0';
           slot1_cs    <= '0';
           slot2_cs    <= '0';
           slot2_cs    <= '0';
           ram_cs      <= '0';
           ram_cs      <= '0';
      if cpu_addr( 15 downto 8 ) = "11111111" then
 
 
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
              cpu_data_in <= rom_data_out;
              cpu_data_in <= rom_data_out;
         dat_cs      <= cpu_vma;              -- write DAT
         dat_cs      <= cpu_vma;              -- write DAT
         rom_cs      <= cpu_vma;              -- read  ROM
         rom_cs      <= cpu_vma;              -- read  ROM
 
 
           --
           --
                -- Sys09Bug Monitor ROM $F000 - $FFFF
                -- Sys09Bug Monitor ROM $F000 - $FFFF
                --
                --
           elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
           elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
                   cpu_data_in <= rom_data_out;
                   cpu_data_in <= rom_data_out;
Line 1019... Line 1031...
                          -- Remaining 6 slots reserved for non SWTPc Peripherals
                          -- Remaining 6 slots reserved for non SWTPc Peripherals
                          --
                          --
                          when others => -- $E0A0 to $E0FF
                          when others => -- $E0A0 to $E0FF
                            null;
                            null;
                     end case;
                     end case;
 
 
                        --
                        --
                        -- XST-3.0 Peripheral Bus goes here
                        -- XST-3.0 Peripheral Bus goes here
                        --      $E100 to $E1FF
                        --      $E100 to $E1FF
                        --      Four devices
                        --      Four devices
                        -- IDE, Ethernet, Slot1, Slot2
                        -- IDE, Ethernet, Slot1, Slot2
Line 1055... Line 1068...
                          -- Nothing else
                          -- Nothing else
                          --
                          --
           when others =>
           when others =>
                            null;
                            null;
           end case;
           end case;
 
 
         --
         --
                        --      $E200 to $EFFF reserved for future use
                        --      $E200 to $EFFF reserved for future use
                        --
                        --
                when others =>
                when others =>
                          null;
                          null;
         end case;
         end case;
 
 
                --
                --
                -- Flex RAM $0C000 - $0DFFF
                -- Flex RAM $0C000 - $0DFFF
                --
                --
                elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
                elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
                   cpu_data_in <= flex_data_out;
                   cpu_data_in <= flex_data_out;
                        flex_cs     <= cpu_vma;
                        flex_cs     <= cpu_vma;
 
 
                --
                --
                -- Everything else is RAM
                -- Everything else is RAM
                --
                --
                else
                else
                   cpu_data_in <= ram_data_out;
                   cpu_data_in <= ram_data_out;
                   ram_cs      <= cpu_vma;
                   ram_cs      <= cpu_vma;
          end if;
          end if;
end process;
 
 
 
 
  end process;
 
 
--
--
-- 16-bit Peripheral Bus
-- 16-bit Peripheral Bus
-- 6809 Big endian
-- 6809 Big endian
-- ISA bus little endian
-- ISA bus little endian
Line 1224... Line 1240...
         cpu_halt   <= '0';
         cpu_halt   <= '0';
         cpu_hold   <= pb_hold or ram_hold;
         cpu_hold   <= pb_hold or ram_hold;
    FLASH_CE_N <= '1';
    FLASH_CE_N <= '1';
end process;
end process;
 
 
 
 
--
--
-- Flash 7 segment LEDS
-- Flash 7 segment LEDS
--
--
my_led_flasher: process( clk_i, rst_i, CountL )
my_led_flasher: process( clk_i, rst_i, CountL )
begin
begin
Line 1244... Line 1259...
-- Generate CPU & Pixel Clock from Memory Clock
-- Generate CPU & Pixel Clock from Memory Clock
--
--
my_prescaler : process( clk_i, clk_count )
my_prescaler : process( clk_i, clk_count )
begin
begin
  if rising_edge( clk_i ) then
  if rising_edge( clk_i ) then
 
 
    if clk_count = 0 then
    if clk_count = 0 then
           clk_count <= CPU_CLK_DIV-1;
           clk_count <= CPU_CLK_DIV-1;
         else
         else
      clk_count <= clk_count - 1;
      clk_count <= clk_count - 1;
         end if;
         end if;
 
 
    if clk_count = 0 then
    if clk_count = 0 then
            clk25 <= '0';
            clk25 <= '0';
    elsif clk_count = (CPU_CLK_DIV/2) then
    elsif clk_count = (CPU_CLK_DIV/2) then
            clk25 <= '1';
            clk25 <= '1';
    end if;
    end if;
 
 
  end if;
  end if;
end process;
end process;
 
 
--
--
-- Reset button and reset timer
-- Reset button and reset timer
Line 1443... Line 1455...
                  ram_wr_req   <= '1';
                  ram_wr_req   <= '1';
      end if;
      end if;
         end if;
         end if;
end process;
end process;
 
 
 
 
 
 
status_leds : process( rst_i, cpu_reset, lock )
status_leds : process( rst_i, cpu_reset, lock )
begin
begin
    S(0) <= rst_i;
    S(0) <= rst_i;
         S(1) <= cpu_reset;
         S(1) <= cpu_reset;
         S(2) <= lock;
         S(2) <= lock;
Line 1473... Line 1483...
--  cpu_addr_o     <= cpu_addr;
--  cpu_addr_o     <= cpu_addr;
--  cpu_data_out_o <= cpu_data_out;
--  cpu_data_out_o <= cpu_data_out;
--  cpu_data_in_o  <= cpu_data_in;
--  cpu_data_in_o  <= cpu_data_in;
--end process;
--end process;
 
 
 
 
end rtl; --===================== End of architecture =======================--
end rtl; --===================== End of architecture =======================--
 
 
 
 
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