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#####################################################
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#
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# XSA-3S1000 Board FPGA pin assignment constraints
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# XSA-3S1000 Board FPGA pin assignment constraints
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#
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#
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#####################################################
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#
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# Clocks
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# Clocks
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#
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#
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#net CLKA loc=T9; # 100MHz
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net CLKA loc=T9 | IOSTANDARD = LVCMOS33 ; # 100MHz
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#net CLKB loc=P8; # 50MHz
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#net CLKB loc=P8 | IOSTANDARD = LVCMOS33 ; # 50MHz
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#net CLKC loc=R9; # ??Mhz
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#net CLKC loc=R9 | IOSTANDARD = LVCMOS33 ; # ??Mhz
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net CLK100 loc=T9; # 100MHz Clock
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#
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#
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# Push button switches
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# Push button switches
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#
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#
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NET SW2_N loc=E11; # active-low pushbutton
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#NET SW1_3_N loc=K2 | IOSTANDARD = LVCMOS33 ; # Flash Block select
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NET SW3_N loc=A13; # active-low pushbutton
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#NET SW1_4_N loc=J4 | IOSTANDARD = LVCMOS33 ; # Flash Block
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NET SW2_N loc=E11 | IOSTANDARD = LVCMOS33 ; # active-low pushbutton
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NET SW3_N loc=A13 | IOSTANDARD = LVCMOS33 ; # active-low pushbutton
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#
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#
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# PS/2 Keyboard
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# PS/2 Keyboard
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net PS2_CLK loc=B16;
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net PS2_DAT loc=E13;
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#
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# Status LED
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#
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#
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net STATUS_LED<0> loc=M6;
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net PS2_CLK loc=B16 | IOSTANDARD = LVCMOS33 ;
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net STATUS_LED<1> loc=M11;
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net PS2_DAT loc=E13 | IOSTANDARD = LVCMOS33 ;
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net STATUS_LED<2> loc=N6;
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net STATUS_LED<3> loc=R7;
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net STATUS_LED<4> loc=P10;
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net STATUS_LED<5> loc=T7;
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net STATUS_LED<6> loc=R10;
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#
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#
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# VGA Outputs
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# VGA Outputs
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#
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#
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NET VGA_BLUE<0> LOC=C9;
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NET VGA_BLUE<0> LOC=C9 | IOSTANDARD = LVCMOS33 ;
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NET VGA_BLUE<1> LOC=E7;
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NET VGA_BLUE<1> LOC=E7 | IOSTANDARD = LVCMOS33 ;
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NET VGA_BLUE<2> LOC=D5;
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NET VGA_BLUE<2> LOC=D5 | IOSTANDARD = LVCMOS33 ;
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NET VGA_GREEN<0> LOC=A8;
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NET VGA_GREEN<0> LOC=A8 | IOSTANDARD = LVCMOS33 ;
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NET VGA_GREEN<1> LOC=A5;
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NET VGA_GREEN<1> LOC=A5 | IOSTANDARD = LVCMOS33 ;
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NET VGA_GREEN<2> LOC=C3;
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NET VGA_GREEN<2> LOC=C3 | IOSTANDARD = LVCMOS33 ;
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NET VGA_RED<0> LOC=C8;
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NET VGA_RED<0> LOC=C8 | IOSTANDARD = LVCMOS33 ;
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NET VGA_RED<1> LOC=D6;
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NET VGA_RED<1> LOC=D6 | IOSTANDARD = LVCMOS33 ;
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NET VGA_RED<2> LOC=B1;
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NET VGA_RED<2> LOC=B1 | IOSTANDARD = LVCMOS33 ;
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NET VGA_HSYNC_N LOC=B7;
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NET VGA_HSYNC_N LOC=B7 | IOSTANDARD = LVCMOS33 ;
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NET VGA_VSYNC_N LOC=D8;
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NET VGA_VSYNC_N LOC=D8 | IOSTANDARD = LVCMOS33 ;
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#
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#
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# Flash memory interface
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# Manually assign locations for the DCMs along the bottom of the FPGA
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#
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# because PAR sometimes places them in opposing corners and that ruins the clocks.
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#net FLASH_A<0> LOC=N5;
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#net FLASH_A<1> LOC=K14;
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#net FLASH_A<2> LOC=K13;
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#net FLASH_A<3> LOC=K12;
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#net FLASH_A<4> LOC=L14;
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#net FLASH_A<5> LOC=M16;
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#net FLASH_A<6> LOC=L13;
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#net FLASH_A<7> LOC=N16;
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#net FLASH_A<8> LOC=N14;
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#net FLASH_A<9> LOC=P15;
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#net FLASH_A<10> LOC=R16;
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#net FLASH_A<11> LOC=P14;
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#net FLASH_A<12> LOC=P13;
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#net FLASH_A<13> LOC=N12;
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#net FLASH_A<14> LOC=T14;
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#net FLASH_A<15> LOC=R13;
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#net FLASH_A<16> LOC=N10;
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#net FLASH_A<17> LOC=M14;
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#net FLASH_A<18> LOC=K3;
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#net FLASH_A<19> LOC=K4;
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#net FLASH_D<8> LOC=T4;
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#net FLASH_D<9> LOC=R5;
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#net FLASH_D<10> LOC=T5;
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#net FLASH_D<11> LOC=P6;
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#net FLASH_D<12> LOC=M7;
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#net FLASH_D<13> LOC=R6;
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#net FLASH_D<14> LOC=N7;
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#net FLASH_D<15> LOC=P7;
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#net FLASH_CE_N LOC=R4;
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#net FLASH_OE_N LOC=P5;
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#net FLASH_WE_N LOC=M13;
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#net FLASH_BYTE_N LOC=T8;
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#net FLASH_RDY LOC=L12;
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#net FLASH_RST_N LOC=P16;
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#
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#
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INST "u1/dllint" LOC="DCM_X0Y0";
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INST "u1/dllext" LOC="DCM_X1Y0";
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# Manually assign locations for the DCMs along the bottom of the FPGA
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# Manually assign locations for the DCMs along the bottom of the FPGA
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# because PAR sometimes places them in opposing corners and that ruins the clocks.
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# because PAR sometimes places them in opposing corners and that ruins the clocks.
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#INST "u2_dllint" LOC="DCM_X0Y0";
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#INST "u2_dllint" LOC="DCM_X0Y0";
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#INST "u2_dllext" LOC="DCM_X1Y0";
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#INST "u2_dllext" LOC="DCM_X1Y0";
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#
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#
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# SDRAM memory pin assignments
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# SDRAM memory pin assignments
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#
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#
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#net SDRAM_clkfb loc=N8; # feedback SDRAM clock after PCB delays
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net SDRAM_clkfb loc=N8 | IOSTANDARD = LVCMOS33 ; # feedback SDRAM clock after PCB delays
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#net SDRAM_clkout loc=E10; # clock to SDRAM
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net SDRAM_clkout loc=E10 | IOSTANDARD = LVCMOS33 ; # clock to SDRAM
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#net SDRAM_CKE loc=D7; # SDRAM clock enable
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net SDRAM_CKE loc=D7 | IOSTANDARD = LVCMOS33 ; # SDRAM clock enable
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#net SDRAM_CS_N loc=B8; # SDRAM chip-select
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net SDRAM_CS_N loc=B8 | IOSTANDARD = LVCMOS33 ; # SDRAM chip-select
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#net SDRAM_RAS_N loc=A9;
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net SDRAM_RAS_N loc=A9 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_CAS_N loc=A10;
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net SDRAM_CAS_N loc=A10 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_WE_N loc=B10;
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net SDRAM_WE_N loc=B10 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_DQMH loc=D9;
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net SDRAM_DQMH loc=D9 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_DQML loc=C10;
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net SDRAM_DQML loc=C10 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_A<0> loc=B5;
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net SDRAM_A<0> loc=B5 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_A<1> loc=A4;
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net SDRAM_A<1> loc=A4 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_A<2> loc=B4;
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net SDRAM_A<2> loc=B4 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_A<3> loc=E6;
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net SDRAM_A<3> loc=E6 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_A<4> loc=E3;
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net SDRAM_A<4> loc=E3 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_A<5> loc=C1;
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net SDRAM_A<5> loc=C1 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_A<6> loc=E4;
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net SDRAM_A<6> loc=E4 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_A<7> loc=D3;
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net SDRAM_A<7> loc=D3 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_A<8> loc=C2;
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net SDRAM_A<8> loc=C2 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_A<9> loc=A3;
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net SDRAM_A<9> loc=A3 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_A<10> loc=B6;
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net SDRAM_A<10> loc=B6 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_A<11> loc=C5;
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net SDRAM_A<11> loc=C5 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_A<12> loc=C6;
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net SDRAM_A<12> loc=C6 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_D<0> loc=C15;
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net SDRAM_D<0> loc=C15 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_D<1> loc=D12;
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net SDRAM_D<1> loc=D12 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_D<2> loc=A14;
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net SDRAM_D<2> loc=A14 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_D<3> loc=B13;
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net SDRAM_D<3> loc=B13 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_D<4> loc=D11;
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net SDRAM_D<4> loc=D11 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_D<5> loc=A12;
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net SDRAM_D<5> loc=A12 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_D<6> loc=C11;
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net SDRAM_D<6> loc=C11 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_D<7> loc=D10;
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net SDRAM_D<7> loc=D10 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_D<8> loc=B11;
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net SDRAM_D<8> loc=B11 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_D<9> loc=B12;
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net SDRAM_D<9> loc=B12 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_D<10> loc=C12;
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net SDRAM_D<10> loc=C12 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_D<11> loc=B14;
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net SDRAM_D<11> loc=B14 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_D<12> loc=D14;
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net SDRAM_D<12> loc=D14 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_D<13> loc=C16;
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net SDRAM_D<13> loc=C16 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_D<14> loc=F12;
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net SDRAM_D<14> loc=F12 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_D<15> loc=F13;
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net SDRAM_D<15> loc=F13 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_BA<0> loc=A7;
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net SDRAM_BA<0> loc=A7 | IOSTANDARD = LVCMOS33 ;
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#net SDRAM_BA<1> loc=C7;
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net SDRAM_BA<1> loc=C7 | IOSTANDARD = LVCMOS33 ;
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#
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# Flash memory interface
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#
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#net FLASH_A<0> LOC=N5 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<1> LOC=K14 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<2> LOC=K13 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<3> LOC=K12 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<4> LOC=L14 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<5> LOC=M16 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<6> LOC=L13 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<7> LOC=N16 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<8> LOC=N14 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<9> LOC=P15 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<10> LOC=R16 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<11> LOC=P14 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<12> LOC=P13 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<13> LOC=N12 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<14> LOC=T14 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<15> LOC=R13 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<16> LOC=N10 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<17> LOC=M14 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<18> LOC=K3 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_A<19> LOC=K4 | IOSTANDARD = LVCMOS33 ;
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#
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#net FLASH_D<0> LOC=M11 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_D<1> LOC=N11 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_D<2> LOC=P10 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_D<3> LOC=R10 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_D<4> LOC=T7 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_D<5> LOC=R7 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_D<6> LOC=N6 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_D<7> LOC=M6 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_D<8> LOC=T4 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_D<9> LOC=R5 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_D<10> LOC=T5 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_D<11> LOC=P6 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_D<12> LOC=M7 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_D<13> LOC=R6 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_D<14> LOC=N7 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_D<15> LOC=P7 | IOSTANDARD = LVCMOS33 ;
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net FLASH_CE_N LOC=R4 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_OE_N LOC=P5 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_WE_N LOC=M13 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_BYTE_N LOC=T8 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_RDY LOC=L12 | IOSTANDARD = LVCMOS33 ;
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#net FLASH_RST_N LOC=P16 | IOSTANDARD = LVCMOS33 ;
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#
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# FPGA Programming interface
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#
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#net FPGA_D<0> LOC=M11 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D0, S1, LED_C
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#net FPGA_D<1> LOC=N11 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D1, S7, LED_DP
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#net FPGA_D<2> LOC=P10 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D2, S4, LED_B
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#net FPGA_D<3> LOC=R10 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D3, S6, LED_A
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#net FPGA_D<4> LOC=T7 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D4, S5, LED_F
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#net FPGA_D<5> LOC=R7 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D5, S3, LED_G
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#net FPGA_D<6> LOC=N6 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D6, S2, LED_E
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#net FPGA_D<7> LOC=M6 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D7, S0, LED_D
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#net FPGA_CCLK LOC=T15 | IOSTANDARD = LVCMOS33 ;
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#net FPGA_DONE LOC=R14 | IOSTANDARD = LVCMOS33 ;
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#net FPGA_INIT_N LOC=N9 | IOSTANDARD = LVCMOS33 ;
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#net FPGA_PROG_N LOC=B3 | IOSTANDARD = LVCMOS33 ;
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#net FPGA_TCK LOC=C14 | IOSTANDARD = LVCMOS33 ;
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#net FPGA_TDI LOC=A2 | IOSTANDARD = LVCMOS33 ;
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#net FPGA_TDI_CSN LOC=R3 | IOSTANDARD = LVCMOS33 ;
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#net FPGA_TDO LOC=A15 | IOSTANDARD = LVCMOS33 ;
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#net FPGA_TDO_WRN LOC=T3 | IOSTANDARD = LVCMOS33 ;
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#net FPGA_TMS LOC=C13 | IOSTANDARD = LVCMOS33 ;
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#net FPGA_TMS_BSY LOC=P9 | IOSTANDARD = LVCMOS33 ;
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#
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# Status LED
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#
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#net S<0> loc=M6 | IOSTANDARD = LVCMOS33 ; # FPGA_D7, LED_D
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#net S<1> loc=M11 | IOSTANDARD = LVCMOS33 ; # FPGA_D0, LED_C
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#net S<2> loc=N6 | IOSTANDARD = LVCMOS33 ; # FPGA_D6, LED_E
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#net S<3> loc=R7 | IOSTANDARD = LVCMOS33 ; # FPGA_D5, LED_G
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#net S<4> loc=P10 | IOSTANDARD = LVCMOS33 ; # FPGA_D2, LED_B
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#net S<5> loc=T7 | IOSTANDARD = LVCMOS33 ; # FPGA_D4, LED_F
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#net S<6> loc=R10 | IOSTANDARD = LVCMOS33 ; # FPGA_D3, LED_A
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#net S<7> loc=N11 | IOSTANDARD = LVCMOS33 ; # FPGA_D1, LED_DP
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#
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#
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# Parallel Port
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# Parallel Port
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#
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#
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#net PPORT_load loc=n14;
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#net PPORT_load loc=N14 | IOSTANDARD = LVCMOS33 ;
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#net PPORT_clk loc=p15;
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#net PPORT_clk loc=P15 | IOSTANDARD = LVCMOS33 ;
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#net PPORT_din<0> loc=r16;
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#net PPORT_din<0> loc=R16 | IOSTANDARD = LVCMOS33 ;
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#net PPORT_din<1> loc=p14;
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#net PPORT_din<1> loc=P14 | IOSTANDARD = LVCMOS33 ;
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#net PPORT_din<2> loc=p13;
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#net PPORT_din<2> loc=P13 | IOSTANDARD = LVCMOS33 ;
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#net PPORT_din<3> loc=n12;
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#net PPORT_din<3> loc=N12 | IOSTANDARD = LVCMOS33 ;
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#net PPORT_dout<0> loc=n5;
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#
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#net PPORT_dout<1> loc=k14;
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#net PPORT_dout<0> loc=N5 | IOSTANDARD = LVCMOS33 ;
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#net PPORT_dout<2> loc=k13;
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#net PPORT_dout<1> loc=K14 | IOSTANDARD = LVCMOS33 ;
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#net PPORT_dout<3> loc=t10;
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#net PPORT_dout<2> loc=K13 | IOSTANDARD = LVCMOS33 ;
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#
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#net PPORT_dout<3> loc=T10 | IOSTANDARD = LVCMOS33 ;
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#
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#
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#net PPORT_d<0> loc=N14; # FLASH_A<8> / PPORT_LOAD
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#net PPORT_d<0> loc=N14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<8> / PPORT_LOAD
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#net PPORT_d<1> loc=P15; # FLASH_A<9> / PPORT_CLK
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#net PPORT_d<1> loc=P15 | IOSTANDARD = LVCMOS33 ; # FLASH_A<9> / PPORT_CLK
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#net PPORT_d<2> loc=R16; # FLASH_A<10> / PPORT_DIN<0>
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#net PPORT_d<2> loc=R16 | IOSTANDARD = LVCMOS33 ; # FLASH_A<10> / PPORT_DIN<0>
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#net PPORT_d<3> loc=P14; # FLASH_A<11> / PPORT_DIN<1>
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#net PPORT_d<3> loc=P14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<11> / PPORT_DIN<1>
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#net PPORT_d<4> loc=P13; # FLASH_A<12> / PPORT_DIN<2>
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#net PPORT_d<4> loc=P13 | IOSTANDARD = LVCMOS33 ; # FLASH_A<12> / PPORT_DIN<2>
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#net PPORT_d<5> loc=N12; # FLASH_A<13> / PPORT_DIN<3>
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#net PPORT_d<5> loc=N12 | IOSTANDARD = LVCMOS33 ; # FLASH_A<13> / PPORT_DIN<3>
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## net PPORT_d<6> loc=T14; # FLASH_A<14>
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##net PPORT_d<6> loc=T14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<14>
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## net PPORT_d<7> loc=R13; # FLASH_A<15>
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##net PPORT_d<7> loc=R13 | IOSTANDARD = LVCMOS33 ; # FLASH_A<15>
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#
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#
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#net PPORT_s<3> loc=N5; # FLASH_A<0> / PPORT_DOUT<0>
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#net PPORT_s<3> loc=N5 | IOSTANDARD = LVCMOS33 ; # FLASH_A<0> / PPORT_DOUT<0>
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#net PPORT_s<4> loc=K14; # FLASH_A<1> / PPORT_DOUT<1>
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#net PPORT_s<4> loc=K14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<1> / PPORT_DOUT<1>
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#net PPORT_s<5> loc=K13; # FLASH_A<2> / PPORT_DOUT<2>
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#net PPORT_s<5> loc=K13 | IOSTANDARD = LVCMOS33 ; # FLASH_A<2> / PPORT_DOUT<2>
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#net PPORT_s<6> loc=T10; # / PPORT_DOUT<3>
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#net PPORT_s<6> loc=T10 | IOSTANDARD = LVCMOS33 ; # / PPORT_DOUT<3>
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#
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#
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########################################################
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########################################################
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#
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#
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# XST3.0 pins
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# XST3.0 pins
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#
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#
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########################################################
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########################################################
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#
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#
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# BAR LED
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# BAR LED
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#
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#
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#net BAR_LED<1> loc=L5; # barled 1
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#net BAR<1> loc=L5 | IOSTANDARD = LVCMOS33 ; # bar led 1, PB_A0
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#net BAR_LED<2> loc=N2; # barled 2
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#net BAR<2> loc=N2 | IOSTANDARD = LVCMOS33 ; # bar led 2, PB_A1
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#net BAR_LED<3> loc=M3; # barled 3
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#net BAR<3> loc=M3 | IOSTANDARD = LVCMOS33 ; # bar led 3, PB_A2
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#net BAR_LED<4> loc=N1; # barled 4
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#net BAR<4> loc=N1 | IOSTANDARD = LVCMOS33 ; # bar led 4, PB_A3
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#net BAR_LED<5> loc=T13; # barled 5
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#net BAR<5> loc=T13 | IOSTANDARD = LVCMOS33 ; # bar led 5, PB_A4
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#net BAR_LED<6> loc=L15; # barled 6
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#net BAR<6> loc=L15 | IOSTANDARD = LVCMOS33 ; # bar led 6, ETHER_IRQ
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#net BAR_LED<7> loc=J13; # barled 7
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#net BAR<7> loc=J13 | IOSTANDARD = LVCMOS33 ; # bar led 7, USB_IRQ_N
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#net BAR_LED<8> loc=H15; # barled 8
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#net BAR<8> loc=H15 | IOSTANDARD = LVCMOS33 ; # bar led 8, IDE_IRQ
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#net BAR<9> loc=J16 | IOSTANDARD = LVCMOS33 ; # bar led 9, SLOT1_IRQ
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#net BAR<10> loc=J14 | IOSTANDARD = LVCMOS33 ; # bar led 10, SLOT2_IRQ
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#
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#
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# Push Buttons
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# Push Buttons
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#
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#
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#net PB1_N loc=H4; # pushbutton PB1
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#net PB1_N loc=H4 | IOSTANDARD = LVCMOS33 ; # Shared with PB_D15
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#net PB2_N loc=L5 | IOSTANDARD = LVCMOS33 ; # Shared with BAR1, PB_A0
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#net PB3_N loc=N2 | IOSTANDARD = LVCMOS33 ; # Shared with BAR2, PB_A1
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#net PB4_N loc=M3 | IOSTANDARD = LVCMOS33 ; # Shared with BAR3, PB_A2
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#
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#
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# RS232 PORT
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# RS232 PORT
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#
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#
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net RS232_TXD loc=J2; # RS232 TD pin 3
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net RS232_TXD loc=J2 | IOSTANDARD = LVCMOS33 ; # RS232 TD pin 3
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net RS232_RXD loc=G5; # RS232 RD pin 2
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net RS232_RXD loc=G5 | IOSTANDARD = LVCMOS33 ; # RS232 RD pin 2
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net RS232_CTS loc=D1; # RS232 CTS
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net RS232_CTS loc=D1 | IOSTANDARD = LVCMOS33 ; # RS232 CTS
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net RS232_RTS loc=F4; # RS232 RTS
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net RS232_RTS loc=F4 | IOSTANDARD = LVCMOS33 ; # RS232 RTS
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#
|
|
# 16 Bit Peripheral Bus
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#
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# 5-bit Peripheral address bus
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net PB_A<0> loc=L5 | IOSTANDARD = LVCMOS33 ; # Shared with BAR1, PB2
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net PB_A<1> loc=N2 | IOSTANDARD = LVCMOS33 ; # Shared with BAR2, PB3
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net PB_A<2> loc=M3 | IOSTANDARD = LVCMOS33 ; # Shared with BAR3, PB4
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net PB_A<3> loc=N1 | IOSTANDARD = LVCMOS33 ; # Shared with BAR4
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net PB_A<4> loc=T13 | IOSTANDARD = LVCMOS33 ; # Shared with BAR5
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|
# 16-bit peripheral data bus
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net PB_D<0> loc=P12 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW1
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net PB_D<1> loc=J1 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW2
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net PB_D<2> loc=H1 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW3
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net PB_D<3> loc=H3 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW4
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net PB_D<4> loc=G2 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW5
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net PB_D<5> loc=K15 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW6
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net PB_D<6> loc=K16 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW7
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net PB_D<7> loc=F15 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW8
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net PB_D<8> loc=E2 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_A
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net PB_D<9> loc=E1 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_B
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net PB_D<10> loc=F3 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_C
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net PB_D<11> loc=F2 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_D
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net PB_D<12> loc=G4 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_E
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net PB_D<13> loc=G3 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_F
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net PB_D<14> loc=G1 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_G
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net PB_D<15> loc=H4 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_DP, PB1
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net PB_RD_N loc=P2 | IOSTANDARD = LVCMOS33 ; # disk I/O read control
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net PB_WR_N loc=R1 | IOSTANDARD = LVCMOS33 ; # disk I/O write control
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#
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#
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# IDE Interface
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# IDE Interface
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#
|
#
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net IDE_IOR_N loc=P2; # disk I/O read control
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net IDE_CS0_N loc=G15 | IOSTANDARD = LVCMOS33 ; # disk register-bank select
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net IDE_IOW_N loc=R1; # disk I/O write control
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net IDE_CS1_N loc=G14 | IOSTANDARD = LVCMOS33 ; # disk register-bank select
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net IDE_CS0_N loc=G15; # disk register-bank select
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net IDE_DMACK_N loc=K1 | IOSTANDARD = LVCMOS33 ; # (out) IDE DMA acknowledge
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net IDE_CS1_N loc=G14; # disk register-bank select
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#net IDE_DMARQ loc=L4 | IOSTANDARD = LVCMOS33 ; # (in) IDE DMA request
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net IDE_A<0> loc=L5; # 3-bit disk register address bus
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#net IDE_IORDY loc=L2 | IOSTANDARD = LVCMOS33 ; # (in) IDE IO ready
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net IDE_A<1> loc=N2;
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#net IDE_IRQ loc=H15 | IOSTANDARD = LVCMOS33 ; # (in) IDE interrupt # shared with BAR8
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net IDE_A<2> loc=M3;
|
|
net IDE_D<0> loc=P12; # 16-bit disk data bus
|
|
net IDE_D<1> loc=J1;
|
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net IDE_D<2> loc=H1;
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net IDE_D<3> loc=H3;
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net IDE_D<4> loc=G2;
|
|
net IDE_D<5> loc=K15;
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net IDE_D<6> loc=K16;
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net IDE_D<7> loc=F15;
|
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net IDE_D<8> loc=E2;
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net IDE_D<9> loc=E1;
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net IDE_D<10> loc=F3;
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net IDE_D<11> loc=F2;
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net IDE_D<12> loc=G4;
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net IDE_D<13> loc=G3;
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net IDE_D<14> loc=G1;
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net IDE_D<15> loc=H4;
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#net IDE_IRQ loc=H15; # IDE interrupt
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|
#net IDE_DMACK_N loc=K1; # IDE DMA acknowledge
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|
#
|
#
|
# Ethernet Controller
|
# Ethernet Controller
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# Disable if not used
|
# Disable if not used
|
#
|
#
|
net ethernet_cs_n loc=G13; # Ethernet chip-enable
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net ether_cs_n loc=G13 | IOSTANDARD = LVCMOS33 ; # (out)Ethernet chip-enable
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net ether_aen loc=E14 | IOSTANDARD = LVCMOS33 ; # (out) Ethernet address enable not
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net ether_bhe_n loc=J3 | IOSTANDARD = LVCMOS33 ; # (out) Ethernet bus high enable
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|
net ether_clk loc=R9 | IOSTANDARD = LVCMOS33 ; # (in) Ethernet clock
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|
net ether_irq loc=L15 | IOSTANDARD = LVCMOS33 ; # (in) Ethernet irq - Shared with BAR6
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|
net ether_rdy loc=M2 | IOSTANDARD = LVCMOS33 ; # (in) Ethernet ready
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|
#
|
|
# Expansion slots
|
|
#
|
|
net slot1_cs_n loc=E15 | IOSTANDARD = LVCMOS33 ; # (out)
|
|
#net slot1_irq loc=J16 | IOSTANDARD = LVCMOS33 ; # (in) Shared with BAR9
|
|
net slot2_cs_n loc=D16 | IOSTANDARD = LVCMOS33 ; # (out)
|
|
#net slot2_irq loc=J14 | IOSTANDARD = LVCMOS33 ; # (in) Shared with BAR10
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|
#
|
|
# Audio codec
|
|
#
|
|
#net audio_lrck loc=R12 | IOSTANDARD = LVCMOS33 ; # (out)
|
|
#net audio_mclk loc=P11 | IOSTANDARD = LVCMOS33 ; # (out)
|
|
#net audio_sclk loc=T12 | IOSTANDARD = LVCMOS33 ; # (out)
|
|
#net audio_sdti loc=M10 | IOSTANDARD = LVCMOS33 ; # (out)
|
|
#net audio_sdto loc=K5 | IOSTANDARD = LVCMOS33 ; # (in)
|
|
#
|
|
# i2c
|
|
#
|
|
#net i2c_scl loc=F5 | IOSTANDARD = LVCMOS33 ; #(out)
|
|
#net i2c_sda loc=D2 | IOSTANDARD = LVCMOS33 ; # (in/out)
|
|
#
|
|
# USB
|
|
#
|
|
#NET USB_CLK LOC=M1 | IOSTANDARD = LVCMOS33 ; # (IN)
|
|
#NET USB_IRQ_N LOC=J13 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with BAR7
|
|
#NET USB_SUSPEND LOC=l3 | IOSTANDARD = LVCMOS33 ; # (IN)
|
|
#
|
|
# VIDEO DIGITIZER
|
|
#
|
|
#NET VIDIN_AVID LOC= | IOSTANDARD = LVCMOS33 ; # (IN)
|
|
#NET VIDIN_CLK LOC=H16 | IOSTANDARD = LVCMOS33 ; # (IN)
|
|
#NET VIDIN_FID LOC= | IOSTANDARD = LVCMOS33 ; # (IN)
|
|
#NET VIDIN_HSYNC LOC= | IOSTANDARD = LVCMOS33 ; # (IN)
|
|
#NET VIDIN_IRQ LOC= | IOSTANDARD = LVCMOS33 ; # (IN)
|
|
#NET VIDIN_VSYNC LOC= | IOSTANDARD = LVCMOS33 ; # (IN)
|
|
#NET VIDIN_Y<0> LOC=H14 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_A
|
|
#NET VIDIN_Y<1> LOC=M4 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_B
|
|
#NET VIDIN_Y<2> LOC=P1 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_C
|
|
#NET VIDIN_Y<3> LOC=N3 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_D
|
|
#NET VIDIN_Y<4> LOC=M15 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_E
|
|
#NET VIDIN_Y<5> LOC=H13 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_F
|
|
#NET VIDIN_Y<6> LOC=G16 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_G
|
|
#NET VIDIN_Y<7> LOC=N15 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_DP
|
#
|
#
|
# Timing Constraints
|
# Timing Constraints
|
#
|
#
|
NET "CLK100" TNM_NET="CLK100";
|
NET "CLKA" TNM_NET="CLKA";
|
TIMESPEC "TS_clk"=PERIOD "CLK100" 10 ns HIGH 50 %;
|
TIMESPEC "TS_clk"=PERIOD "CLKA" 10 ns HIGH 50 %;
|
TIMESPEC "TS_clk"=PERIOD "CLKA" 10 ns HIGH 50 %;
|
TIMESPEC "TS_clk"=PERIOD "CLKA" 10 ns HIGH 50 %;
|
