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--===========================================================================--
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--===========================================================================--
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-- --
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-- TESTBENCH testbench4 - CPU09 Testbench. --
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-- --
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--===========================================================================--
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--
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--
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-- MC6809 Microprocessor Test Bench 4
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-- File name : Testbench4.vhd
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-- Test Software - SBUG ROM
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--
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--
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-- Purpose : cpu09 Microprocessor Test Bench 4
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-- Contains SBUG ROM
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--
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--
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-- John Kent 12st April 2003
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-- Dependencies : ieee.Std_Logic_1164
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_arith
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-- ieee.numeric_std
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--
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--
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-- Version 1.1 - 25th Jan 2004 - John Kent
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-- Uses : cpu09 (..\VHDL\cpu09.vhd) CPU core
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-- removed "test_alu" and "test_cc"
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-- ram_2k (..\Spartan3\ram2k_b16.vhd) 2KB block RAM
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-- mon_rom (..\Spartan3\sbug_rom2k_b16.vhd) 2KB SBUG block ROM
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--
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--
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-- Author : John E. Kent
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-- dilbert57@opencores.org
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--
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--
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-------------------------------------------------------------------------------
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-- Copyright (C) 2003 - 2011 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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-- --
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-- Revision History --
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-- --
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--===========================================================================--
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--
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-- Rev Date Author Changes
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-- 0.1 2003-04-12 John Kent First version
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-- 1.0 2003-09-06 John Kent Initial release to Opencores.org
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-- 1.1 2004-02-25 John kent removed test_alu and test_cc signals from CPU component.
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-- 1.2 2011-10-09 John Kent renamed address to addr on CPU component, updated header
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--
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--===========================================================================--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity my_testbench is
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entity my_testbench4 is
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end my_testbench;
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end my_testbench4;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for memio Controller Unit
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-- Architecture for memio Controller Unit
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture behavior of my_testbench is
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architecture behavior of my_testbench4 is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Signals
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-- Signals
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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signal cpu_irq : std_Logic;
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signal cpu_irq : std_Logic;
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signal cpu_firq : std_logic;
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signal cpu_firq : std_logic;
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port (
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port (
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clk: in std_logic;
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clk: in std_logic;
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rst: in std_logic;
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rst: in std_logic;
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rw: out std_logic; -- Asynchronous memory interface
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rw: out std_logic; -- Asynchronous memory interface
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vma: out std_logic;
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vma: out std_logic;
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address: out std_logic_vector(15 downto 0);
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addr: out std_logic_vector(15 downto 0);
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data_in: in std_logic_vector(7 downto 0);
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data_in: in std_logic_vector(7 downto 0);
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data_out: out std_logic_vector(7 downto 0);
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data_out: out std_logic_vector(7 downto 0);
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halt: in std_logic;
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halt: in std_logic;
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hold: in std_logic;
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hold: in std_logic;
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irq: in std_logic;
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irq: in std_logic;
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firq: in std_logic
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firq: in std_logic
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);
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);
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end component;
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end component;
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component sbug_rom
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component mon_rom
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Port (
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Port (
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MEMclk : in std_logic;
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clk : in std_logic;
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MEMaddr : in std_logic_vector (10 downto 0);
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rst : in std_logic;
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MEMrdata : out std_logic_vector (7 downto 0)
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cs : in std_logic;
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rw : in std_logic;
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addr : in std_logic_vector (10 downto 0);
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data_in : in std_logic_vector (7 downto 0);
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data_out : out std_logic_vector (7 downto 0)
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);
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);
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end component;
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end component;
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component block_ram
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component ram_2k
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Port (
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Port (
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MEMclk : in std_logic;
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clk : in std_logic;
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MEMcs : in std_logic;
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rst : in std_logic;
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MEMrw : in std_logic;
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cs : in std_logic;
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MEMaddr : in std_logic_vector (10 downto 0);
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addr : in std_logic_vector (10 downto 0);
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MEMrdata : out std_logic_vector (7 downto 0);
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rw : in std_logic;
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MEMwdata : in std_logic_vector (7 downto 0)
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data_in : in std_logic_vector (7 downto 0);
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data_out : out std_logic_vector (7 downto 0)
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);
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);
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end component;
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end component;
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begin
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begin
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my_cpu : cpu09 port map (
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my_cpu : cpu09 port map (
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clk => SysClk,
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clk => SysClk,
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rst => cpu_reset,
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rst => cpu_reset,
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rw => cpu_rw,
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rw => cpu_rw,
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vma => cpu_vma,
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vma => cpu_vma,
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address => cpu_addr(15 downto 0),
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addr => cpu_addr(15 downto 0),
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data_in => cpu_data_in,
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data_in => cpu_data_in,
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data_out => cpu_data_out,
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data_out => cpu_data_out,
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halt => cpu_halt,
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halt => cpu_halt,
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hold => cpu_hold,
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hold => cpu_hold,
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irq => cpu_irq,
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irq => cpu_irq,
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nmi => cpu_nmi,
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nmi => cpu_nmi,
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firq => cpu_firq
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firq => cpu_firq
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);
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);
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my_ram : block_ram port map (
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my_rom : mon_rom port map (
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MEMclk => SysClk,
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clk => SysClk,
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MEMcs => ram_cs,
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rst => cpu_reset,
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MEMrw => cpu_rw,
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cs => ram_cs,
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MEMaddr => cpu_addr(10 downto 0),
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rw => cpu_rw,
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MEMrdata => ram_data_out,
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addr => cpu_addr(10 downto 0),
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MEMwdata => cpu_data_out
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data_in => cpu_data_out,
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data_out => rom_data_out
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);
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);
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my_rom : sbug_rom port map (
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MEMclk => SysClk,
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my_ram : ram_2k port map (
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MEMaddr => cpu_addr(10 downto 0),
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clk => SysClk,
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MEMrdata => rom_data_out
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rst => cpu_reset,
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cs => ram_cs,
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rw => cpu_rw,
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addr => cpu_addr(10 downto 0),
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data_in => cpu_data_out,
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data_out => ram_data_out
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);
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);
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-- *** Test Bench - User Defined Section ***
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-- *** Test Bench - User Defined Section ***
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tb : PROCESS
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tb : PROCESS
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variable count : integer;
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variable count : integer;
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