OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [Testbench/] [testbench4.vhd] - Diff between revs 66 and 122

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 66 Rev 122
Line 1... Line 1...
--===========================================================================--
--===========================================================================--
 
--                                                                           --
 
--             TESTBENCH    testbench4 - CPU09 Testbench.                    --
 
--                                                                           --
 
--===========================================================================--
--
--
-- MC6809 Microprocessor Test Bench 4
-- File name      : Testbench4.vhd
-- Test Software - SBUG ROM
 
--
--
 
-- Purpose        : cpu09 Microprocessor Test Bench 4
 
--                  Contains SBUG ROM
--
--
-- John Kent 12st April 2003
-- Dependencies   : ieee.Std_Logic_1164
 
--                  ieee.std_logic_unsigned
 
--                  ieee.std_logic_arith
 
--                  ieee.numeric_std
--
--
-- Version 1.1 - 25th Jan 2004 - John Kent
-- Uses           : cpu09    (..\VHDL\cpu09.vhd)              CPU core
-- removed "test_alu" and "test_cc"
--                  ram_2k   (..\Spartan3\ram2k_b16.vhd)      2KB block RAM
 
--                  mon_rom  (..\Spartan3\sbug_rom2k_b16.vhd) 2KB SBUG block ROM
--
--
 
-- Author         : John E. Kent
 
--                  dilbert57@opencores.org      
--
--
-------------------------------------------------------------------------------
--  Copyright (C) 2003 - 2011 John Kent
 
--
 
--  This program is free software: you can redistribute it and/or modify
 
--  it under the terms of the GNU General Public License as published by
 
--  the Free Software Foundation, either version 3 of the License, or
 
--  (at your option) any later version.
 
--
 
--  This program is distributed in the hope that it will be useful,
 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 
--  GNU General Public License for more details.
 
--
 
--  You should have received a copy of the GNU General Public License
 
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
--
 
--===========================================================================--
 
--                                                                           --
 
--                                Revision History                           --
 
--                                                                           --
 
--===========================================================================--
 
--
 
-- Rev  Date       Author     Changes
 
-- 0.1  2003-04-12 John Kent  First version
 
-- 1.0  2003-09-06 John Kent  Initial release to Opencores.org
 
-- 1.1  2004-02-25 John kent  removed test_alu and test_cc signals from CPU component.
 
-- 1.2  2011-10-09 John Kent  renamed address to addr on CPU component, updated header
 
--
 
--===========================================================================--
 
 
library ieee;
library ieee;
   use ieee.std_logic_1164.all;
   use ieee.std_logic_1164.all;
   use IEEE.STD_LOGIC_ARITH.ALL;
   use IEEE.STD_LOGIC_ARITH.ALL;
   use ieee.numeric_std.all;
   use ieee.numeric_std.all;
 
 
entity my_testbench is
entity my_testbench4 is
end my_testbench;
end my_testbench4;
 
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture behavior of my_testbench is
architecture behavior of my_testbench4 is
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Signals
  -- Signals
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  signal cpu_irq    : std_Logic;
  signal cpu_irq    : std_Logic;
  signal cpu_firq   : std_logic;
  signal cpu_firq   : std_logic;
Line 48... Line 87...
  port (
  port (
         clk:        in std_logic;
         clk:        in std_logic;
    rst:             in std_logic;
    rst:             in std_logic;
    rw:      out        std_logic;              -- Asynchronous memory interface
    rw:      out        std_logic;              -- Asynchronous memory interface
    vma:             out        std_logic;
    vma:             out        std_logic;
    address:  out       std_logic_vector(15 downto 0);
    addr:     out       std_logic_vector(15 downto 0);
    data_in:  in        std_logic_vector(7 downto 0);
    data_in:  in        std_logic_vector(7 downto 0);
         data_out: out std_logic_vector(7 downto 0);
         data_out: out std_logic_vector(7 downto 0);
         halt:     in  std_logic;
         halt:     in  std_logic;
         hold:     in  std_logic;
         hold:     in  std_logic;
         irq:      in  std_logic;
         irq:      in  std_logic;
Line 60... Line 99...
         firq:     in  std_logic
         firq:     in  std_logic
  );
  );
end component;
end component;
 
 
 
 
component sbug_rom
component mon_rom
    Port (
    Port (
       MEMclk   : in  std_logic;
       clk      : in  std_logic;
       MEMaddr  : in  std_logic_vector (10 downto 0);
                 rst      : in  std_logic;
       MEMrdata : out std_logic_vector (7 downto 0)
                 cs       : in  std_logic;
 
                 rw       : in  std_logic;
 
       addr     : in  std_logic_vector (10 downto 0);
 
       data_in  : in  std_logic_vector (7 downto 0);
 
       data_out : out std_logic_vector (7 downto 0)
    );
    );
end component;
end component;
 
 
component block_ram
component ram_2k
    Port (
    Port (
       MEMclk   : in  std_logic;
       clk      : in  std_logic;
       MEMcs    : in  std_logic;
       rst      : in  std_logic;
                 MEMrw    : in  std_logic;
       cs       : in  std_logic;
       MEMaddr  : in  std_logic_vector (10 downto 0);
       addr     : in  std_logic_vector (10 downto 0);
       MEMrdata : out std_logic_vector (7 downto 0);
       rw       : in  std_logic;
       MEMwdata : in  std_logic_vector (7 downto 0)
       data_in  : in  std_logic_vector (7 downto 0);
 
       data_out : out std_logic_vector (7 downto 0)
    );
    );
end component;
end component;
 
 
begin
begin
my_cpu : cpu09  port map (
my_cpu : cpu09  port map (
         clk         => SysClk,
         clk         => SysClk,
    rst      => cpu_reset,
    rst      => cpu_reset,
    rw       => cpu_rw,
    rw       => cpu_rw,
    vma       => cpu_vma,
    vma       => cpu_vma,
    address   => cpu_addr(15 downto 0),
    addr      => cpu_addr(15 downto 0),
    data_in   => cpu_data_in,
    data_in   => cpu_data_in,
         data_out  => cpu_data_out,
         data_out  => cpu_data_out,
         halt      => cpu_halt,
         halt      => cpu_halt,
         hold      => cpu_hold,
         hold      => cpu_hold,
         irq       => cpu_irq,
         irq       => cpu_irq,
         nmi       => cpu_nmi,
         nmi       => cpu_nmi,
         firq      => cpu_firq
         firq      => cpu_firq
  );
  );
 
 
 
 
my_ram : block_ram port map (
my_rom : mon_rom port map (
       MEMclk   => SysClk,
       clk      => SysClk,
                 MEMcs    => ram_cs,
       rst      => cpu_reset,
                 MEMrw    => cpu_rw,
                 cs       => ram_cs,
       MEMaddr  => cpu_addr(10 downto 0),
                 rw       => cpu_rw,
       MEMrdata => ram_data_out,
       addr     => cpu_addr(10 downto 0),
       MEMwdata => cpu_data_out
       data_in  => cpu_data_out,
 
       data_out => rom_data_out
    );
    );
 
 
my_rom : sbug_rom port map (
 
       MEMclk   => SysClk,
my_ram : ram_2k port map (
       MEMaddr  => cpu_addr(10 downto 0),
       clk      => SysClk,
       MEMrdata => rom_data_out
       rst      => cpu_reset,
 
                 cs       => ram_cs,
 
                 rw       => cpu_rw,
 
       addr     => cpu_addr(10 downto 0),
 
       data_in  => cpu_data_out,
 
       data_out => ram_data_out
    );
    );
 
 
  -- *** Test Bench - User Defined Section ***
  -- *** Test Bench - User Defined Section ***
   tb : PROCESS
   tb : PROCESS
        variable count : integer;
        variable count : integer;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.