-----------------------------------------------------------------
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--===========================================================================--
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-- --
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-- BaudClock.vhd - Synthesizable Baud Rate Clock Divider --
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-- --
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--===========================================================================--
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--
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--
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-- ACIA Clock Divider for System09
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-- File name : BaudClock.vhd
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--
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-- Purpose : Implements a baud rate clock divider for a 6850 compatible
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-- Asynchronous Communications Interface Adapter
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--
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-- Dependencies : ieee.std_logic_1164
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-- ieee.std_logic_arith
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-- ieee.std_logic_unsigned
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-- ieee.numeric_std
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-- unisim.vcomponents
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--
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-- Author : John E. Kent
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--
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-- Email : dilbert57@opencores.org
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--
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-- Web : http://opencores.org/project,system09
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--
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-- BaudClock.vhd is baud rate clock divider for a 6850 compatible ACIA core.
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--
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-- Copyright (C) 2003 - 2010 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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-- --
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-- Revision History --
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-- --
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--===========================================================================--
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--
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-- Revision Name Date Description
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-- 0.1 John E. Kent unknown Initial version
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-- 1.0 John E. Kent 30th May 2010 Added GPL Header
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--
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--
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-----------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use ieee.std_logic_arith.all;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library unisim;
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library unisim;
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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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entity ACIA_Clock is
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entity ACIA_Clock is
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generic (
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generic (
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SYS_Clock_Frequency : integer;
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SYS_Clock_Frequency : integer;
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BAUD_Clock_Frequency : integer
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BAUD_Clock_Frequency : integer
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);
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);
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port(
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port(
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clk : in Std_Logic; -- System Clock input
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clk : in Std_Logic; -- System Clock input
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ACIA_Clk : out Std_Logic -- ACIA Clock output
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ACIA_Clk : out Std_Logic -- ACIA Clock output
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);
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);
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end ACIA_Clock;
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end ACIA_Clock;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for ACIA_Clock
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-- Architecture for ACIA_Clock
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture rtl of ACIA_Clock is
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architecture rtl of ACIA_Clock is
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constant full_cycle : integer := (SYS_Clock_Frequency / BAUD_Clock_Frequency) - 1;
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constant full_cycle : integer := (SYS_Clock_Frequency / BAUD_Clock_Frequency) - 1;
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constant half_cycle : integer := (full_cycle / 2) - 1;
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constant half_cycle : integer := (full_cycle / 2) - 1;
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--
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--
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-- Baud Rate Clock Divider
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-- Baud Rate Clock Divider
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--
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--
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-- 25MHz / 27 = 926,000 KHz = 57,870Bd * 16
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-- 25MHz / 27 = 926,000 KHz = 57,870Bd * 16
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-- 50MHz / 54 = 926,000 KHz = 57,870Bd * 16
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-- 50MHz / 54 = 926,000 KHz = 57,870Bd * 16
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--
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--
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my_baud_clock: process( SysClk )
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my_baud_clock: process( SysClk )
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begin
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begin
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if(SysClk'event and SysClk = '0') then
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if(SysClk'event and SysClk = '0') then
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if( BaudCount = 53 ) then
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if( BaudCount = 53 ) then
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baudclk <= '0';
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baudclk <= '0';
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BaudCount <= "000000";
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BaudCount <= "000000";
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else
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else
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if( BaudCount = 26 ) then
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if( BaudCount = 26 ) then
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baudclk <='1';
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baudclk <='1';
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else
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else
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baudclk <=baudclk;
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baudclk <=baudclk;
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end if;
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end if;
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BaudCount <= BaudCount + 1;
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BaudCount <= BaudCount + 1;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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