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[/] [System09/] [trunk/] [rtl/] [VHDL/] [SevenSegment.vhd] - Diff between revs 66 and 99

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--===========================================================================--
--===========================================================================--
--
--                                                                           --
--  S Y N T H E Z I A B L E    Dynamic Address Translation Registers
--  SevenSegment.vhd - Synthesizable Multiplex Seven Segment LED Driver      --
--
--                                                                           --
--  www.OpenCores.Org - December 2002
--===========================================================================--
--  This core adheres to the GNU public license  
 
--
--
-- File name      : SevenSegment.vhd
-- File name      : SevenSegment.vhd
--
--
-- entity name    : SevenSegment
--  Entity name    : SevenSegment
--
--
-- Purpose        : 4 x 8 bit lathes to display 7 segments
-- Purpose        : 4 x 8 bit lathes to display 7 segments
 
--                   Multiplexes segment registers across 4 displays.
 
--                   For use on the Digilent Spartan 3 Starter Board
--                  
--                  
-- Dependencies   : ieee.Std_Logic_1164
--  Dependencies   : ieee.std_logic_1164
--                  ieee.std_logic_unsigned
--                  ieee.std_logic_unsigned
 
--                   unisim.vcomponents
--
--
-- Author         : John E. Kent      
-- Author         : John E. Kent      
--
--
--===========================================================================----
--  Email          : dilbert57@opencores.org      
 
--
 
--  Web            : http://opencores.org/project,system09
 
--
 
--  SevenSegment.vhd is a multiplexed seven segment LED display driver written in VHDL
 
-- 
 
--  Copyright (C) 2004 - 2010 John Kent
--
--
-- Revision History:
--  This program is free software: you can redistribute it and/or modify
 
--  it under the terms of the GNU General Public License as published by
 
--  the Free Software Foundation, either version 3 of the License, or
 
--  (at your option) any later version.
--
--
-- Date          Revision  Author 
--  This program is distributed in the hope that it will be useful,
-- 19 Oct 2004   0.1       John Kent
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 
--  GNU General Public License for more details.
--
--
-- 21 Nov 2006   0.2       John Kent
--  You should have received a copy of the GNU General Public License
-- Inverted segment registers 
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
-- so '0' in segment registers switches segment OFF
--
 
--===========================================================================--
 
--                                                                           --
 
--                              Revision  History                            --
 
--                                                                           --
 
--===========================================================================--
 
--
 
-- Version  Author        Date               Description
 
-- 0.1      John Kent     19 Oct 2004        Initial version
 
-- 0.2      John Kent     21 Nov 2006        Inverted segment registers 
 
--                                           so '0' in segment registers 
 
--                                           switches segment OFF
 
-- 0.3      John Kent     31 May 2010        Updated Header and GPL.
--
--
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
 
library unisim;
 
   use unisim.vcomponents.all;
 
 
entity seven_segment is
entity seven_segment is
        port (
        port (
         clk       : in  std_logic;
         clk       : in  std_logic;
    rst       : in  std_logic;
    rst       : in  std_logic;
    cs        : in  std_logic;
    cs        : in  std_logic;

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