| Line 1... |
Line 1... |
--===========================================================================----
|
--===========================================================================--
|
--
|
-- --
|
-- S Y N T H E Z I A B L E epp - Enhanced Parallel Port
|
-- Synthesizable Enhance Parallel Port --
|
--
|
-- --
|
-- www.OpenCores.Org - September 2003
|
--===========================================================================--
|
-- This core adheres to the GNU public license
|
|
--
|
--
|
-- File name : epp.vhd
|
-- File name : epp.vhd
|
--
|
--
|
-- Purpose : Simple Parallel Port for System09
|
-- Entity name : epp
|
--
|
--
|
-- Dependencies : ieee.Std_Logic_1164
|
-- Purpose : Implements an Enhanced Parallel Port Interface
|
-- ieee.std_logic_unsigned
|
|
--
|
--
|
-- Uses : None
|
-- Dependencies : ieee.std_logic_1164
|
|
-- ieee.std_logic_unsigned
|
|
-- unisim.vcomponents
|
--
|
--
|
-- Author : John E. Kent
|
-- Author : John E. Kent
|
-- dilbert57@opencores.org
|
|
--
|
--
|
--===========================================================================----
|
-- Email : dilbert57@opencores.org
|
--
|
--
|
-- Revision History:
|
-- Web : http://opencores.org/project,system09
|
--===========================================================================--
|
|
--
|
--
|
-- Version 0.1 - 6th Sep 2008
|
-- Description : Register Memory Map
|
-- Generated from ioport.vhd
|
|
--
|
--
|
--===========================================================================
|
-- Address MSB LSB
|
|
-- Bit: 7 6 5 4 3 2 1 0
|
|
-- Base+$00 (SPP Data port) Write Pin: 9 8 7 6 5 4 3 2
|
|
-- Base+$01 (SPP Status port) Read Pin: ~11 10 12 13 15
|
|
-- Base+$02 (SPP Control port) Write Pin: ~17 16 ~14 ~1
|
|
-- Base+$03 (EPP Address port) R/W
|
|
-- Base+$04 (EPP Data port) R/W
|
|
--
|
|
-- ~ indicates a hardware inversion of the bit.
|
--
|
--
|
-- Parallel printer port pin assignment
|
-- Parallel printer port pin assignment
|
--
|
--
|
-- Pin No (DB25) SPP Signal EPP Signal Direction Register Bit Inverted
|
-- Pin No (DB25) SPP Signal EPP Signal Direction Register Bit Inverted
|
-- 1 nStrobe Write_n Out Control-0 Yes
|
-- 1 nStrobe Write_n Out Control-0 Yes
|
| Line 41... |
Line 46... |
-- 9 Data7 Data7 In/Out Data-7 No
|
-- 9 Data7 Data7 In/Out Data-7 No
|
-- 10 nAck Interrupt In Status-6 No
|
-- 10 nAck Interrupt In Status-6 No
|
-- 11 Busy Wait In Status-7 Yes
|
-- 11 Busy Wait In Status-7 Yes
|
-- 12 Paper-Out Spare In Status-5 No
|
-- 12 Paper-Out Spare In Status-5 No
|
-- 13 Select Spare In Status-4 No
|
-- 13 Select Spare In Status-4 No
|
--
|
|
-- 14 Linefeed Data_Strobe_n Out Control-1 Yes
|
-- 14 Linefeed Data_Strobe_n Out Control-1 Yes
|
-- 15 nError Spare In Status-3 No
|
-- 15 nError Spare In Status-3 No
|
-- 16 nInitialize Reset Out Control-2 No
|
-- 16 nInitialize Reset Out Control-2 No
|
-- 17 nSelect-Printer Addr_Strobe_n Out Control-3 Yes
|
-- 17 nSelect-Printer Addr_Strobe_n Out Control-3 Yes
|
-- 18-25 Ground Ground - - -
|
-- 18-25 Ground Ground - - -
|
--
|
--
|
-- Address MSB LSB
|
-- Copyright (C) 2008 - 2010 John Kent
|
-- Bit: 7 6 5 4 3 2 1 0
|
|
-- Base (SPP Data port) Write Pin: 9 8 7 6 5 4 3 2
|
|
-- Base+1 (SPP Status port) Read Pin: ~11 10 12 13 15
|
|
-- Base+2 (SPP Control port) Write Pin: ~17 16 ~14 ~1
|
|
-- Base+3 (EPP Address port) R/W
|
|
-- Base+4 (EPP Data port) R/W
|
|
--
|
--
|
-- ~ indicates a hardware inversion of the bit.
|
-- This program is free software: you can redistribute it and/or modify
|
|
-- it under the terms of the GNU General Public License as published by
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
|
-- (at your option) any later version.
|
|
--
|
|
-- This program is distributed in the hope that it will be useful,
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
-- GNU General Public License for more details.
|
|
--
|
|
-- You should have received a copy of the GNU General Public License
|
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
--
|
|
--
|
|
--===========================================================================--
|
|
-- --
|
|
-- Revision History --
|
|
-- --
|
|
--===========================================================================--
|
|
--
|
|
-- Revision Author Date Description
|
|
--
|
|
-- 0.1 John E. Kent 2008-09-06 initial version generated from ioport.vhd
|
|
-- 0.2 John E. Kent 2010-08-09 updated header and added GPL
|
--
|
--
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
|
library unisim;
|
|
use unisim.vcomponents.all;
|
|
|
entity epp is
|
entity epp is
|
port (
|
port (
|
|
--
|
|
-- CPU Interface Signals
|
|
--
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector(2 downto 0);
|
addr : in std_logic_vector(2 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
epp_data : out std_logic_vector(7 downto 0);
|
irq : out std_logic;
|
|
hold : out std_logic;
|
|
--
|
|
-- Parallel Port Interface Signals
|
|
--
|
epp_stat : in std_logic_vector(7 downto 3);
|
epp_stat : in std_logic_vector(7 downto 3);
|
epp_ctrl : out std_logic_vector(3 downto 0);
|
epp_ctrl : out std_logic_vector(3 downto 0);
|
hold : out std_logic;
|
epp_data : out std_logic_vector(7 downto 0)
|
irq : out std_logic
|
|
);
|
);
|
end;
|
end;
|
|
|
architecture rtl of epp is
|
architecture rtl of epp is
|
|
|
