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--===========================================================================--
--===========================================================================--
 
--                                                                           --
 
--             Synthesizable Hardware Breakpoint Trap                        --
 
--                                                                           --
 
--===========================================================================--
--
--
--  S Y N T H E Z I A B L E    Timer   C O R E
--  File name      : trap.vhd
--
 
--  www.OpenCores.Org - May 2003
 
--  This core adheres to the GNU public license  
 
--
 
-- File name      : Trap.vhd
 
--
--
-- entity name    : trap
--  Entity name    : trap
--
--
-- Purpose        : Implements a 8 bit address and data comparitor module
--  Purpose        : Implements a 8 bit address and data hardware breakpoint comparator
 
--                   which generates an interrupt output on qualified match conditions
--
--
-- Dependencies   : ieee.Std_Logic_1164
-- Dependencies   : ieee.Std_Logic_1164
--                  ieee.std_logic_unsigned
--                  ieee.std_logic_unsigned
--
--
-- Author         : John E. Kent      
-- Author         : John E. Kent      
--
--
--===========================================================================----
--  Email          : dilbert57@opencores.org      
--
 
-- Revision History:
 
--
--
-- Date:          Revision         Author
--  Web            : http://opencores.org/project,system09
-- 5 May 2003     0.1              John Kent
 
--
--
--===========================================================================----
--  Description    : Register Memory Map
--
--
-- Register Memory Map
--                   Base + $00 - Address Comparitor High Byte
 
--                   Base + $01 - Address Comparitor Low byte
 
--                   Base + $02 - Data    Comparitor
 
--                   Base + $03 - Control Comparitor
 
--                   Base + $04 - Address Qualifier High Byte
 
--                   Base + $05 - Address Qualifier Low byte
 
--                   Base + $06 - Data    Qualifier
 
--                   Base + $07 - Control Qualifier
 
--
 
--                   Address, Data and Control signals 
 
--                   must match in the Comparitor registers 
 
--                   Matches are qualified by setting a bit 
 
--                   in the Qualifier registers
--
--
-- $00 - Address Comparitor High Byte
--                   Control Comparitor / Control Qualify (write)
-- $01 - Address Comparitor Low byte
 
-- $02 - Data    Comparitor
 
-- $03 - Control Comparitor
 
-- $04 - Address Qualifier High Byte
 
-- $05 - Address Qualifier Low byte
 
-- $06 - Data    Qualifier
 
-- $07 - Control Qualifier
 
--
 
-- Address, Data and Control signals must match in the Comparitor registers 
 
-- Matches are qualified by setting a bit in the Qualifier registers
 
--
 
-- Control Comparitor / Qualify (write)
 
-- b0 - r/w        1=read  0=write
-- b0 - r/w        1=read  0=write
-- b1 - vma        1=valid 0=invalid
-- b1 - vma        1=valid 0=invalid
-- b7 - irq output 1=match 0=mismatch
-- b7 - irq output 1=match 0=mismatch
--
--
-- Control Qualifier Read
-- Control Qualifier Read
-- b7 - match flag
-- b7 - match flag
--
--
 
--  Copyright (C) 2003 - 2010 John Kent
 
--
 
--  This program is free software: you can redistribute it and/or modify
 
--  it under the terms of the GNU General Public License as published by
 
--  the Free Software Foundation, either version 3 of the License, or
 
--  (at your option) any later version.
 
--
 
--  This program is distributed in the hope that it will be useful,
 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 
--  GNU General Public License for more details.
 
--
 
--  You should have received a copy of the GNU General Public License
 
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
--
 
--===========================================================================--
 
--                                                                           --
 
--                             Revision History                              --
 
--                                                                           --
 
--===========================================================================--
 
-- Version Author     Date        Description
 
-- 0.1     John Kent  2003-05-05  Initial version
 
-- 0.2     John kent  2010-08-09  Updated header & GPL information
 
--
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
entity trap is
entity trap is
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           ((comp_ctrl(0)    xor rw        ) and qual_ctrl(0)    ) or
           ((comp_ctrl(0)    xor rw        ) and qual_ctrl(0)    ) or
           ((comp_ctrl(1)    xor vma       ) and qual_ctrl(1)    );
           ((comp_ctrl(1)    xor vma       ) and qual_ctrl(1)    );
 
 
   match := not ( match_addr_hi or match_addr_lo or match_data or match_ctrl);
   match := not ( match_addr_hi or match_addr_lo or match_data or match_ctrl);
 
 
    if clk'event and clk = '0' then
 
           if rst = '1' then
           if rst = '1' then
                  match_flag <= '0';
                  match_flag <= '0';
      elsif cs = '1' and rw = '0' then
    elsif clk'event and clk = '0' then
 
      if cs = '1' and rw = '0' then
                  match_flag <= '0';
                  match_flag <= '0';
      else
      else
                  if match = comp_ctrl(7) then
                  if match = comp_ctrl(7) then
                    match_flag <= '1';
                    match_flag <= '1';
                  else
 
                    match_flag <= match_flag;
 
                  end if;
                  end if;
 
 
                end if;
                end if;
    end if;
    end if;
         irq <= match_flag and qual_ctrl(7);
         irq <= match_flag and qual_ctrl(7);
  end process;
  end process;
 
 

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