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[/] [System09/] [trunk/] [src/] [sys09bug/] [mon_rom_vhd] - Diff between revs 89 and 97

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Rev 89 Rev 97
Line 16... Line 16...
       clk   : in  std_logic;
       clk   : in  std_logic;
       rst   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (11 downto 0);
       addr  : in  std_logic_vector (11 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       data_out : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
       data_in : in  std_logic_vector (7 downto 0)
    );
    );
end mon_rom;
end mon_rom;
 
 
architecture rtl of mon_rom is
architecture rtl of mon_rom is
 
 
Line 38... Line 38...
       clk   : in  std_logic;
       clk   : in  std_logic;
       rst   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       data_out : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
       data_in : in  std_logic_vector (7 downto 0)
    );
    );
end component;
end component;
 
 
component SYS09BUG_F800
component SYS09BUG_F800
    Port (
    Port (
       clk   : in  std_logic;
       clk   : in  std_logic;
       rst   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       data_out : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
       data_in : in  std_logic_vector (7 downto 0)
    );
    );
end component;
end component;
 
 
begin
begin
 
 
Line 63... Line 63...
       clk   => clk,
       clk   => clk,
       rst   => rst,
       rst   => rst,
       cs    => cs0,
       cs    => cs0,
       rw    => rw,
       rw    => rw,
       addr  => addr(10 downto 0),
       addr  => addr(10 downto 0),
       wdata => wdata,
       data_in => data_in,
       rdata => rdata0
       data_out => rdata0
    );
    );
 
 
   addr_f800 : SYS09BUG_F800 port map (
   addr_f800 : SYS09BUG_F800 port map (
       clk   => clk,
       clk   => clk,
       rst   => rst,
       rst   => rst,
       cs    => cs1,
       cs    => cs1,
       rw    => rw,
       rw    => rw,
       addr  => addr(10 downto 0),
       addr  => addr(10 downto 0),
       wdata => wdata,
       data_in => data_in,
       rdata => rdata1
       data_out => rdata1
    );
    );
 
 
    my_mon : process ( rw, addr, cs, rdata0, rdata1 )
    my_mon : process ( rw, addr, cs, rdata0, rdata1 )
    begin
    begin
       we    <= not rw;
       we    <= not rw;
       case addr(11) is
       case addr(11) is
           when '0' =>
           when '0' =>
               cs0   <= cs;
               cs0   <= cs;
               cs1   <= '0';
               cs1   <= '0';
               rdata <= rdata0;
               data_out <= rdata0;
           when '1' =>
           when '1' =>
               cs0   <= '0';
               cs0   <= '0';
               cs1   <= cs;
               cs1   <= cs;
               rdata <= rdata1;
               data_out <= rdata1;
           when others =>
           when others =>
               null;
               null;
       end case;
       end case;
    end process;
    end process;
 
 

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