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[/] [System09/] [trunk/] [src/] [sys09bug/] [mon_rom_vhd] - Diff between revs 66 and 87

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Rev 66 Rev 87
--
--
-- SYS09BUG Monitor Program
-- SYS09BUG Monitor Program
-- v1.0 - 21 November 2006 - John Knet
-- v1.0 - 21 November 2006 - John Knet
--
--
-- v1.1 - 22 december 2006 - John Kent
-- v1.1 - 22 december 2006 - John Kent
--        made into 4K ROM/RAM.
--        made into 4K ROM/RAM.
--
--
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
library unisim;
        use unisim.vcomponents.all;
        use unisim.vcomponents.all;
entity mon_rom is
entity mon_rom is
    Port (
    Port (
       clk   : in  std_logic;
       clk   : in  std_logic;
                 rst   : in  std_logic;
       rst   : in  std_logic;
                 cs    : in  std_logic;
       cs    : in  std_logic;
                 rw    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (11 downto 0);
       addr  : in  std_logic_vector (11 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
       wdata : in  std_logic_vector (7 downto 0)
    );
    );
end mon_rom;
end mon_rom;
architecture rtl of mon_rom is
architecture rtl of mon_rom is
  signal we     : std_logic;
  signal we     : std_logic;
  signal cs0    : std_logic;
  signal cs0    : std_logic;
  signal cs1    : std_logic;
  signal cs1    : std_logic;
  signal dp0    : std_logic;
  signal dp0    : std_logic;
  signal dp1    : std_logic;
  signal dp1    : std_logic;
  signal rdata0 : std_logic_vector(7 downto 0);
  signal rdata0 : std_logic_vector(7 downto 0);
  signal rdata1 : std_logic_vector(7 downto 0);
  signal rdata1 : std_logic_vector(7 downto 0);
component SYS09BUG_F000
component SYS09BUG_F000
    Port (
    Port (
       clk   : in  std_logic;
       clk   : in  std_logic;
       rst   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
       wdata : in  std_logic_vector (7 downto 0)
    );
    );
end component;
end component;
component SYS09BUG_F800
component SYS09BUG_F800
    Port (
    Port (
       clk   : in  std_logic;
       clk   : in  std_logic;
       rst   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
       wdata : in  std_logic_vector (7 downto 0)
    );
    );
end component;
end component;
begin
begin
   addr_f000 : SYS09BUG_F000 port map (
   addr_f000 : SYS09BUG_F000 port map (
       clk   => clk,
       clk   => clk,
       rst   => rst,
       rst   => rst,
       cs    => cs0,
       cs    => cs0,
       rw    => rw,
       rw    => rw,
       addr  => addr(10 downto 0),
       addr  => addr(10 downto 0),
       wdata => wdata,
       wdata => wdata,
       rdata => rdata0
       rdata => rdata0
    );
    );
   addr_f800 : SYS09BUG_F800 port map (
   addr_f800 : SYS09BUG_F800 port map (
       clk   => clk,
       clk   => clk,
       rst   => rst,
       rst   => rst,
       cs    => cs1,
       cs    => cs1,
       rw    => rw,
       rw    => rw,
       addr  => addr(10 downto 0),
       addr  => addr(10 downto 0),
       wdata => wdata,
       wdata => wdata,
       rdata => rdata1
       rdata => rdata1
    );
    );
my_mon : process ( rw, addr, cs, rdata0, rdata1 )
    my_mon : process ( rw, addr, cs, rdata0, rdata1 )
begin
    begin
         we    <= not rw;
       we    <= not rw;
         case addr(11) is
       case addr(11) is
         when '0' =>
           when '0' =>
           cs0   <= cs;
               cs0   <= cs;
                cs1   <= '0';
               cs1   <= '0';
                rdata <= rdata0;
               rdata <= rdata0;
    when '1' =>
           when '1' =>
           cs0   <= '0';
               cs0   <= '0';
                cs1   <= cs;
               cs1   <= cs;
                rdata <= rdata1;
               rdata <= rdata1;
    when others =>
           when others =>
      null;
               null;
    end case;
    end case;
 
 
end process;
end process;
end architecture rtl;
end architecture rtl;
 
 

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