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// Altera or its authorized distributors. Please refer to the
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Sun Oct 19 14:48:51 2014"
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// CREATED "Tue Feb 23 22:17:29 2016"
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module alu_flags(
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module alu_flags(
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ctl_flags_oe,
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ctl_flags_oe,
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ctl_flags_bus,
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ctl_flags_bus,
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ctl_flags_alu,
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ctl_flags_alu,
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ctl_flags_use_cf2,
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ctl_flags_use_cf2,
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ctl_flags_hf2_we,
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ctl_flags_hf2_we,
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ctl_flags_nf_clr,
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ctl_flags_nf_clr,
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ctl_alu_zero_16bit,
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ctl_alu_zero_16bit,
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clk,
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clk,
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ctl_flags_cf2_sel,
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ctl_flags_cf2_sel_shift,
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ctl_flags_cf2_sel_daa,
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flags_sf,
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flags_sf,
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flags_zf,
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flags_zf,
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flags_hf,
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flags_hf,
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flags_pf,
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flags_pf,
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flags_cf,
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flags_cf,
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input wire ctl_flags_use_cf2;
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input wire ctl_flags_use_cf2;
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input wire ctl_flags_hf2_we;
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input wire ctl_flags_hf2_we;
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input wire ctl_flags_nf_clr;
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input wire ctl_flags_nf_clr;
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input wire ctl_alu_zero_16bit;
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input wire ctl_alu_zero_16bit;
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input wire clk;
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input wire clk;
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input wire [1:0] ctl_flags_cf2_sel;
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input wire ctl_flags_cf2_sel_shift;
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input wire ctl_flags_cf2_sel_daa;
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output wire flags_sf;
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output wire flags_sf;
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output wire flags_zf;
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output wire flags_zf;
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output wire flags_hf;
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output wire flags_hf;
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output wire flags_pf;
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output wire flags_pf;
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output wire flags_cf;
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output wire flags_cf;
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output reg flags_hf2;
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output reg flags_hf2;
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inout wire [7:0] db;
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inout wire [7:0] db;
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reg flags_xf;
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reg flags_xf;
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reg flags_yf;
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reg flags_yf;
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wire [1:0] sel;
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wire SYNTHESIZED_WIRE_0;
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wire SYNTHESIZED_WIRE_0;
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reg DFFE_inst_latch_hf;
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reg DFFE_inst_latch_hf;
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wire SYNTHESIZED_WIRE_1;
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wire SYNTHESIZED_WIRE_1;
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wire SYNTHESIZED_WIRE_2;
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wire SYNTHESIZED_WIRE_2;
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wire SYNTHESIZED_WIRE_3;
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wire SYNTHESIZED_WIRE_3;
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alu_mux_4 b2v_inst_mux_cf2(
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alu_mux_4 b2v_inst_mux_cf2(
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.in0(alu_core_cf_out),
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.in0(alu_core_cf_out),
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.in1(shift_cf_out),
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.in1(shift_cf_out),
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.in2(daa_cf_out),
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.in2(daa_cf_out),
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.in3(SYNTHESIZED_WIRE_37),
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.in3(SYNTHESIZED_WIRE_37),
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.sel(ctl_flags_cf2_sel),
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.sel(sel),
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.out(SYNTHESIZED_WIRE_28));
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.out(SYNTHESIZED_WIRE_28));
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assign sel[0] = ctl_flags_cf2_sel_shift;
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assign sel[1] = ctl_flags_cf2_sel_daa;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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