| Line 18... |
Line 18... |
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module data_pins(
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module data_pins(
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bus_db_pin_oe,
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bus_db_pin_oe,
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bus_db_pin_re,
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bus_db_pin_re,
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ctl_bus_db_we,
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ctl_bus_db_we,
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bus_db_oe,
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clk,
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clk,
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ctl_bus_db_oe,
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D,
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D,
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db
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db
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);
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);
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input wire bus_db_pin_oe;
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input wire bus_db_pin_oe;
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input wire bus_db_pin_re;
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input wire bus_db_pin_re;
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input wire ctl_bus_db_we;
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input wire ctl_bus_db_we;
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input wire bus_db_oe;
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input wire clk;
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input wire clk;
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input wire ctl_bus_db_oe;
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inout wire [7:0] D;
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inout wire [7:0] D;
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inout wire [7:0] db;
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inout wire [7:0] db;
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reg [7:0] dout;
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reg [7:0] dout;
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wire [7:0] SYNTHESIZED_WIRE_0;
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wire [7:0] SYNTHESIZED_WIRE_0;
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| Line 60... |
Line 60... |
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assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4;
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assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4;
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assign SYNTHESIZED_WIRE_2 = ctl_bus_db_we | bus_db_pin_re;
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assign SYNTHESIZED_WIRE_2 = ctl_bus_db_we | bus_db_pin_re;
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assign db[7] = bus_db_oe ? dout[7] : 1'bz;
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assign db[7] = ctl_bus_db_oe ? dout[7] : 1'bz;
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assign db[6] = bus_db_oe ? dout[6] : 1'bz;
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assign db[6] = ctl_bus_db_oe ? dout[6] : 1'bz;
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assign db[5] = bus_db_oe ? dout[5] : 1'bz;
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assign db[5] = ctl_bus_db_oe ? dout[5] : 1'bz;
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assign db[4] = bus_db_oe ? dout[4] : 1'bz;
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assign db[4] = ctl_bus_db_oe ? dout[4] : 1'bz;
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assign db[3] = bus_db_oe ? dout[3] : 1'bz;
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assign db[3] = ctl_bus_db_oe ? dout[3] : 1'bz;
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assign db[2] = bus_db_oe ? dout[2] : 1'bz;
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assign db[2] = ctl_bus_db_oe ? dout[2] : 1'bz;
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assign db[1] = bus_db_oe ? dout[1] : 1'bz;
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assign db[1] = ctl_bus_db_oe ? dout[1] : 1'bz;
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assign db[0] = bus_db_oe ? dout[0] : 1'bz;
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assign db[0] = ctl_bus_db_oe ? dout[0] : 1'bz;
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assign D[7] = bus_db_pin_oe ? dout[7] : 1'bz;
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assign D[7] = bus_db_pin_oe ? dout[7] : 1'bz;
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assign D[6] = bus_db_pin_oe ? dout[6] : 1'bz;
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assign D[6] = bus_db_pin_oe ? dout[6] : 1'bz;
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assign D[5] = bus_db_pin_oe ? dout[5] : 1'bz;
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assign D[5] = bus_db_pin_oe ? dout[5] : 1'bz;
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assign D[4] = bus_db_pin_oe ? dout[4] : 1'bz;
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assign D[4] = bus_db_pin_oe ? dout[4] : 1'bz;
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