| Line 7... |
Line 7... |
|
|
// ----------------- CLOCKS AND RESET -----------------
|
// ----------------- CLOCKS AND RESET -----------------
|
// Define one full T-clock cycle delay
|
// Define one full T-clock cycle delay
|
`define T #2
|
`define T #2
|
bit clk = 1;
|
bit clk = 1;
|
initial repeat (24) #1 clk = ~clk;
|
initial repeat (26) #1 clk = ~clk;
|
|
reg nreset;
|
|
|
// ----------------------------------------------------
|
// ----------------------------------------------------
|
// Bi-directional bus that can also be tri-stated
|
// Bi-directional bus that can also be tri-stated
|
reg [15:0] abusw; // Drive it using this bus
|
reg [15:0] abusw; // Drive it using this bus
|
wire [15:0] abus; // Read it using this bus
|
wire [15:0] abus; // Read it using this bus
|
| Line 25... |
Line 26... |
|
|
// ----------------- INC/DEC -----------------
|
// ----------------- INC/DEC -----------------
|
reg ctl_inc_dec; // Perform decrement (1) or increment (0)
|
reg ctl_inc_dec; // Perform decrement (1) or increment (0)
|
reg ctl_inc_limit6; // Limit increment to 6 bits (for incrementing IR)
|
reg ctl_inc_limit6; // Limit increment to 6 bits (for incrementing IR)
|
reg ctl_inc_cy; // Address increment, carry in value (+/-1 or 0)
|
reg ctl_inc_cy; // Address increment, carry in value (+/-1 or 0)
|
reg ctl_inc_zero; // Output zero from the incrementer
|
reg clrpc; // Force zero (to clear PC/IR)
|
|
|
// ----------------- OUTPUT/STATUS -----------------
|
// ----------------- OUTPUT/STATUS -----------------
|
wire address_is_1; // Signals when the final address is 1
|
wire address_is_1; // Signals when the final address is 1
|
|
|
// ----------------- TEST -------------------
|
// ----------------- TEST -------------------
|
`define CHECK(arg) \
|
`define CHECK(arg) \
|
assert(address==arg);
|
assert(address==arg);
|
|
|
initial begin
|
initial begin
|
|
nreset = 0;
|
abusw = 'z;
|
abusw = 'z;
|
ctl_al_we = 0;
|
ctl_al_we = 0;
|
ctl_bus_inc_oe = 0;
|
ctl_bus_inc_oe = 0;
|
ctl_inc_dec = 0;
|
ctl_inc_dec = 0;
|
ctl_inc_limit6 = 0;
|
ctl_inc_limit6 = 0;
|
ctl_inc_cy = 0;
|
ctl_inc_cy = 0;
|
ctl_inc_zero = 0;
|
clrpc = 0;
|
ctl_apin_mux = 0;
|
ctl_apin_mux = 0;
|
ctl_apin_mux2 = 0;
|
ctl_apin_mux2 = 0;
|
|
|
//------------------------------------------------------------
|
//------------------------------------------------------------
|
|
`T nreset = 1;
|
|
|
|
//------------------------------------------------------------
|
// Perform a simple increment and decrement
|
// Perform a simple increment and decrement
|
`T abusw = 16'h1234;
|
`T abusw = 16'h1234;
|
ctl_al_we = 1; // Write value to the latch
|
ctl_al_we = 1; // Write value to the latch
|
ctl_apin_mux = 1; // Output incrementer to the address bus
|
ctl_apin_mux = 1; // Output incrementer to the address bus
|
ctl_inc_cy = 1; // +1 show "1235"
|
ctl_inc_cy = 1; // +1 show "1235"
|
